Power efficient watchdog service

• US 20100332902A1
• Filed: 06/30/2009
• Published: 12/30/2010
• Est. Priority Date: 06/30/2009
• Status: Abandoned Application

• Current Assignee: Bruce L. Fleming, Rajesh Banginwar, Rajesh Kapoor
• Original Assignee: Bruce L. Fleming, Rajesh Banginwar, Rajesh Kapoor
• Inventors: Fleming, Bruce L., Kapoor, Rajesh, Banginwar, Rajesh
• Application Number:
  US12/459,295
• Publication Number:
  US 20100332902A1
• Time in Patent Office: Days
• US Class Current: 714/23
• CPC Class Codes: G06F 11/0715 in a system implementing multitasking multitasking per se G06F9/46
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/34 Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An electronic device comprises a first processor, a computer readable memory medium and logic instructions stored in the computer readable medium which, when executed by the first processor, configure the first processor to implement a watchdog module which monitors an operating status of one or more critical processes executing on the first processor and implements a recovery process when the one or more of the critical processes executing on the first processor fails. The device further comprises a system controller unit coupled to the first processor by a communication bus, wherein system controller unit activates the watchdog module periodically and only when the first processor is in at least one predetermined power state. Other embodiments may be described.

Claims

1. An electronic device, comprising:

a first processor;

a computer readable memory medium; and

logic instructions stored in the computer readable medium which, when executed by the first processor, configure the first processor to implement a watchdog module which;

monitors an operating status of one or more critical processes executing on the first processor; and

implements a recovery process when the one or more of the critical processes executing on the first processor fails; and

a system controller unit coupled to the first processor by a communication bus, wherein system controller unit activates the watchdog module periodically and only when the first processor is in at least one predetermined power state.

2. The electronic device of claim 1, wherein:

the first processor comprises a central processing unit (CPU); and

the system controller unit is implemented as a low-power controller on a second processor, separate from the first processor.

3. The electronic device of claim 2, wherein the system controller unit:

maintains a watchdog activation timer; and

activates the watchdog activation timer only when the first processor is in at least one predetermined power state.

4. The electronic device of claim 3, wherein the system controller unit reboots the electronic device when the watchdog activation timer passes a threshold.

5. The electronic device of claim 4, wherein:

the system controller unit generates an interrupt prior to the watchdog activation timer reaching the threshold.

6. The electronic device of claim 5, wherein, in response to the interrupt:

the first processor is activated; and

a watchdog service executing on the first processor checks to determine whether one or more critical processes are executing on the first processor.

7. The electronic device of claim 6, wherein, in response to a determination that one or more critical processes executing on the first processor have failed, the watchdog service reboots the electronic device.

8. The electronic device of claim 6, wherein, in response to a determination that one or more critical processes executing on the first processor are executing successfully, the watchdog service resets a threshold timer for the watchdog module.

9. The electronic device of claim 6, wherein, in response to a determination that one or more critical processes executing on the first processor have failed, the watchdog service resets a threshold timer for the watchdog module.

10. The electronic device of claim 3, wherein the watchdog activation timer is paused when the electronic device transitions from an active state to a low-power sleep state.

11. The electronic device of claim 3, wherein the watchdog activation timer is started when the electronic device transitions from a low-power sleep state to an active state.

12. A method to implement a power efficient watchdog service in an electronic device, comprising:

on a first processor;

monitoring an operating status of one or more critical processes executing on a first processor; and

implementing a recovery process when the one or more of the critical processes executing on the first processor fails; and

activating, on a system controller unit coupled to the first processor by a communication bus a watchdog module periodically and only when the first processor is in at least one predetermined power state.

13. The method of claim 12, wherein:

the first processor comprises a central processing unit (CPU); and

the system controller unit is implemented as a low-power controller on a second processor, separate from the first processor.

14. The method of claim 13, wherein the system controller unit:

maintains a watchdog activation timer; and

activates the watchdog activation timer only when the first processor is in at least one predetermined power state.

15. The method of claim 14, wherein the system controller unit reboots the electronic device when the watchdog activation timer passes a threshold.

16. The method of claim 15, wherein:

the system controller unit generates an interrupt prior to the watchdog activation timer reaching the threshold.

17. The method of claim 16, wherein, in response to the interrupt:

the first processor is activated; and

a watchdog service executing on the first processor checks to determine whether one or more critical processes are executing on the first processor.

18. The method of claim 17, wherein, in response to a determination that one or more critical processes executing on the first processor have failed, the watchdog service reboots the electronic device.

19. The method of claim 17, wherein, in response to a determination that one or more critical processes executing on the first processor are executing successfully, the watchdog service resets a threshold timer for the watchdog module.

20. The method of claim 17, wherein, in response to a determination that one or more critical processes executing on the first processor have failed, the watchdog service resets a threshold timer for the watchdog module.

21. The method of claim 14, wherein the watchdog activation timer is paused when the electronic device transitions from an active state to a low-power sleep state.

22. The method of claim 14, wherein the watchdog activation timer is started when the electronic device transitions from a low-power sleep state to an active state.