VERTICAL BUS CIRCUITS

• US 20110001357A1
• Filed: 12/23/2009
• Published: 01/06/2011
• Est. Priority Date: 01/06/2009
• Status: Active Grant

• Current Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Original Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Inventors: LIU, Liusheng, LI, Guoxing
• Granted Patent: US 8,227,944 B2
• Time in Patent Office: Days
• US Class Current: 307/38
• CPC Class Codes: G01R 31/396 Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
• CPC Class Codes: H01M 10/425 Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing printed circuits H05K1/00
• CPC Class Codes: H01M 10/482 for several batteries or cells simultaneously or sequentially
• CPC Class Codes: H01M 10/486 for measuring temperature
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

A vertical bus circuit includes multiple devices for transmitting signals between the bus devices. The multiple devices share multiple common voltage levels. Each of the devices includes a bus block and two input/output (I/O) devices powered by a first voltage level and a second voltage level of the common voltage levels, respectively. The bus block enables signal transmission between the two I/O devices, and the common voltage levels enable the signal transmission between the devices.

Claims

1. A vertical bus circuit, comprising:

a plurality of bus blocks operable for transmitting signals between said bus blocks, wherein said bus blocks share a plurality of common voltage levels, wherein each of said bus blocks comprises a signal path and two input/output (I/O) devices powered by a first voltage level and a second voltage level of said common voltage levels, respectively, and wherein said signal path enables signal transmission between said two I/O devices and said common voltage levels enable said signal transmission between said bus blocks.

2. The circuit of claim 1, wherein said signal path comprises an upward signal path and a downward signal path and wherein said upward signal path and said down signal path share said two I/O devices.

3. The circuit of claim 1, wherein each of said bus blocks is coupled to a group of cells in a battery, and said bus blocks are operable for transmitting said signals in a battery management system.

4. The circuit of claim 3, wherein said signals indicate the statuses of said cells.

5. The circuit of claim 3, wherein the voltage of at least one cell in said group of cells is used as each of said common voltage levels.

6. The circuit of claim 3, wherein each of said bus blocks further comprises a voltage regulator, and wherein each of said common voltage levels is provided by the voltage at the positive terminal of one cell in said group of cells and the output voltage of said voltage regulator.

7. The circuit of claim 1, wherein said signal path comprises a differential circuit operable for transmitting said signals.

8. A battery management system, comprising:

a plurality of devices couplable to a battery having a plurality of cells, said devices operable for assessing the status of said cells, wherein each of said devices is coupled to a group of said cells and said devices use different voltages; and

a control unit coupled to a first device of said devices and operable for communicating with a destination device of said devices via said control unit, said first device, a first plurality of said devices, and said destination device;

wherein said first plurality of devices uses voltages that are between a voltage used by said first device and a voltage used by said destination device.

9. The system of claim 8, wherein said devices are powered by said cells, and wherein said first device comprises a device powered by a cell that has the lowest voltage level among said cells.

10. The system of claim 8, wherein said devices share a plurality of common voltage levels, and wherein each of said common voltage levels is configured to enable communication between a first device of said devices and a second device of said devices that share said common voltage level.

11. The system of claim 10, wherein each of said devices has two input/output (I/O) devices, wherein a first port of said two I/O devices is powered by a first common voltage level of said common voltage levels and a second port of said two I/O ports is powered by a second common voltage level of said common voltage levels.

12. The system of claim 11, wherein each of said devices comprises a bus block operable for transmitting signals between said two I/O devices.

13. The system of claim 12, wherein said bus block comprises an upward signal path and a downward signal path, and wherein said upward signal path and said down signal path share said two I/O devices.

14. The system of claim 10, wherein each of said common voltage levels is provided by a voltage of at least one cell in said group of cells.

15. The system of claim 10, wherein each of said devices comprises a voltage regulator, and wherein each of said common voltage levels is provided by the voltage at the positive terminal of one cell in said group of cells and the output voltage of said voltage regulator.

16. The system of claim 8, wherein said devices further comprise a plurality of analog-to-digital converters (ADC) and wherein said common voltage levels are configured to diagnosis said ADCs.

17. The system of claim 12, wherein said bus block comprises a differential circuit operable for transmitting said signals.

18. The system of claim 8, wherein each of said devices comprises a bus engine, and said bus engine uses a default line for signal transmission and wherein a backup line replaces said default line if said default line becomes unavailable.

19. A method for enabling signal transmission, said method comprising:

transmitting a signal between a first common voltage level to a second common voltage level in a first bus block of a plurality of bus blocks; and

transmitting said signal between said first bus block and a second bus block of said bus blocks, wherein said first and second bus blocks share said second common voltage level.

20. The method of claim 19, further comprising:

issuing said signal from a control unit; and

transmitting said signal between said control unit and said first bus block.

21. The method of claim 19, further comprising:

accessing the statuses of cells in a battery; and

converting said statuses to said signal using a converter.

22. The method of claim 19, further comprising:

converting a first reference voltage to a first value using an accurate first converter;

converting said first reference voltage to a second value using a second converter; and

comparing said first value to said second value for diagnosing said second converter.

23. The method of claim 22, further comprising:

calibrating said second converter according to a result of said comparing;

converting a second reference voltage to a third value using said second converter;

converting said second reference voltage to a fourth value using a third converter; and

comparing said third value to said fourth value for diagnosing said third converter.

24. The method of claim 23, wherein said second reference voltage comprises said second common voltage level.

25. The method of claim 19 wherein said first common voltage level is useful for powering a first I/O device in said first bus block and wherein said second common voltage level is useful for powering a second I/O device in said first bus block.