CIRCUIT FOR CAPACITIVE TOUCH APPLICATIONS

• US 20110001492A1
• Filed: 09/14/2010
• Published: 01/06/2011
• Est. Priority Date: 10/24/2008
• Status: Active Grant

• Current Assignee: Advanced Silicon SA
• Original Assignee: Advanced Silicon SA
• Inventors: Vuadens, François, Nys, Olivier, Ballan, Hussein, Chappatte, Norman
• Granted Patent: US 8,970,227 B2
• Time in Patent Office: Days
• US Class Current: 324/658
• CPC Class Codes: H03M 1/123 Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
• CPC Class Codes: H03M 1/46 with digital/analogue converter for supplying reference values to converter

Abstract

A circuit for capacitive touch applications comprising

• • a charge integrator
  • a low pass-filter
  • a correlated double sampler comprising an input capacitor
  • a sampler and holder
  • an analog to digital converter
  • said low pass-filter having a cut-off frequency lower than the Nyquist frequency of the sampler and holder
  • said low pass filter comprising said input capacitor and a serial resistor.

Claims

1. A circuit for capacitive touch applications comprising

a charge integrator

a low pass-filter

a correlated double sampler comprising an input capacitor

a sampler and holder

an analog to digital converter

said low pass-filter having a cut-off frequency lower than the Nyquist frequency of the sampler and holder,

said low pass filter comprising said input capacitor and a serial resistor.

2. The circuit of claim 1, wherein said low-pass filter and said correlated double sampler are integrated in a single block.

3. The circuit of claim 1, wherein said analog to digital converter is a switched capacitor analog to digital converter.

4. The circuit of claim 3, wherein said analog to digital converter is a multistage analog to digital converter comprising a first stage and further stages.

5. The circuit of claim 4, wherein said first stage comprises a successive approximation register and a feedback digital to analog converter.

6. The circuit of claim 5, wherein said sampler and holder is integrated in said first stage of said analog-to-digital converter.

7. The circuit of claim 6, wherein an amplifier is shared between said sampler and holder and said first stage of said analog-to-digital converter.

8. The circuit of claim 4, wherein said further stages comprise a pipeline ADC or an algorithmic ADC or two or more cascaded components, each cascaded component being an algorithmic ADC.

9. The circuit of claim 1, wherein said charge integrator comprises a charge sense amplifier and means for integrating a charge against a virtual ground.

10. The circuit claim 1, comprising means for optimising the range of said charge integrator and/or of said single block by offset variation.

11. The circuit of claim 4, wherein said low pass filter, said correlated doubler sampler, said sampler and holder and said first stage of said analog to digital converter are integrated in a single block.

12. The circuit of claim 11, wherein a capacitor is shared between said sampler and holder integrated in said first stage of said analog-to-digital converter and said single block integrating said low-pass filter and said correlated double sampler.

13. The circuit of claim 11, wherein said single block comprises

said serial resistor connected between the output of said charge integrator and said input capacitor

said input capacitor connected between said serial resistor and an input switch

said input switch connected between said input capacitor and a virtual ground of an amplifier

said amplifier

a reset switch for said amplifier, connected between said virtual ground and the output of said amplifier

a feedback capacitor, connected between said virtual ground and a node, said node being connected to a first pre-charging switch, to a second feedback switch and a third switch, said third switch being connected to a digital to analog converter

said first pre-charging switch, said second feedback switch, said third switch and said digital to analog converter

a comparator connected to the output of said amplifier.

14. The circuit of claim 13, wherein said amplifier integrates the functions of the amplifiers of both said correlated double sampler and said first stage of said analog to digital converter.

15. The circuit of claim 14, further comprising

a residue capacitor connected between the virtual ground of said amplifier and a node, said node being connected to a fourth pre-charging switch and a fifth switch, said fifth switch being connected to the output of said amplifier

said fourth pre-charging switch and said fifth switch.

16. A method for the circuit of claim 13 comprising the following phases:

an initialisation phase, during which;

said input capacitor is pre-charged to a voltage of a first sample by closing said input switch

said amplifier is reset by closing said reset switch

said feedback capacitor is pre-charged to an initialisation voltage by closing said pre-charging switch

a charge integration phase, during which;

said voltage of a first sample on said input capacitor changes into a voltage of a second sample

said input switch, said reset switch and said pre-charging switch are opened

said feedback capacitor is switched in feedback of said amplifier by closing said feedback switch in order to generate a first voltage to be converted proportional to the difference between the voltage of said second sample and the voltage of said first sample

an analog to digital conversion phase, during which

said feedback switch is opened

said feedback capacitor is switched to a second voltage generated by said digital-to-analog converter in order to generate a third voltage proportional to the difference between said first voltage and said second voltage.

17. A method for the circuit of claim 15 comprising the following phases:

an initialisation phase, during which;

said input capacitor is pre-charged to a voltage of a first sample by closing said input switch

said amplifier is reset by closing said reset switch

said feedback capacitor is pre-charged to an initialisation voltage by closing said pre-charging switch

a charge integration phase, during which;

said voltage of a first sample on said input capacitor changes into a voltage of a second sample

said input switch, said reset switch and said pre-charging switch are opened

said feedback capacitor is switched in feedback of said amplifier by closing said feedback switch in order to generate a first voltage to be converted proportional to the difference between the voltage of said second sample and the voltage of said first sample

an analog to digital conversion phase, during which

said feedback switch is opened

said feedback capacitor is switched to a second voltage generated by said digital-to-analog converter in order to generate a third voltage proportional to the difference between said first voltage and said second voltage.

18. The method of the previous claim wherein said initialisation phase further comprises the following step

said residue capacitor is pre-charged to a residue initialisation voltage by closing said fourth pre-charging switch

said charge integration phase further comprises the following step

said fourth pre-charging switch is opened

said analog to digital conversion phase further comprises the following step

said residue capacitor is switched in feedback of said amplifier instead of said feedback capacitor by closing said fifth switch.

19. The method of claim 18, said analog to digital conversion phase further comprises

a coarse quantisation phase, during which said feedback capacitor remains again in the feedback path of said amplifier, after said input capacitor has been disconnected, before switching said residue capacitor in feedback of said amplifier.

20. A capacitive touch device comprising:

an array comprising a first number of rows and a second number of columns of sensing capacitors;

means for generating an input signal and for addressing said input signal to each of said rows at a row scan rate

said second number of circuits according to claim 1.

21. The capacitive touch device of claim 20, wherein each of the ADCs in said circuits comprises a DAC, said capacitive touch device comprising a plurality of voltage reference unit providing a plurality of reference voltages to said DACs of several ADCs of said ADCs.

22. The capacitive touch device circuit of claim 21, wherein said reference unit is a resistive ladder.

23. The capacitive touch device of claim 21, wherein said reference unit includes one reference ladder that is common between said circuits and having a plurality of taps, said reference voltage being present at said taps.

24. The capacitive touch device of claim 20, wherein said ADCs are arranged to generate a residue signal which is encoded by one or several further ADC stages.