LIGHT EMITTING DIODE HAVING VERTICAL TOPOLOGY AND METHOD OF MAKING THE SAME

• US 20110003416A1
• Filed: 09/13/2010
• Published: 01/06/2011
• Est. Priority Date: 06/23/2006
• Status: Active Grant

• Current Assignee: Suzhou Lekin Semiconductor Company Limited
• Original Assignee: LG Electronics, Inc. (LG Corporation), LG Innotek Company Limited (LG Corporation)
• Inventors: JANG, Jun Ho, Park, Jong Kook, Lee, Jeong Soo, Kim, Sun Jung, Choi, Jae Wan, Bae, Duk Kyu, Cho, Hyun Kyong
• Granted Patent: US 8,039,281 B2
• Time in Patent Office: Days
• US Class Current: 438/29
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 2933/0083 Periodic patterns for optical field-shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/04 with a quantum effect structure or superlattice, e.g. tunnel junction
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/40 Materials therefor
• CPC Class Codes: H01L 33/405 Reflective materials
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating

Abstract

An LED having vertical topology and a method of making the same is capable of improving a luminous efficiency and reliability, and is also capable of achieving mass productivity. The method includes forming a semiconductor layer on a substrate; forming a first electrode on the semiconductor layer; forming a supporting layer on the first electrode; generating an acoustic stress wave at the interface between the substrate and semiconductor layer, thereby separating the substrate from the semiconductor layer; and forming a second electrode on the semiconductor layer exposed by the separation of the substrate.

Claims

1. A method of making a light emitting diode (LED) having vertical topology, comprising:

forming a semiconductor layer on a substrate;

forming a first electrode on the semiconductor layer;

forming a supporting layer on the first electrode;

separating the substrate from the semiconductor layer by generating an acoustic stress wave at a portion between the substrate and the semiconductor layer; and

forming a second electrode on a surface of the semiconductor layer exposed by the separation of the substrate.

2. The method according to claim 1, further comprising etching a chip separation region of the semiconductor layer to form a trench.

3. The method according to claim 1, wherein the first electrode comprises at least one of Ni, W, Ti, Pt, Au, Pd, Cu, Al, Cr, and Ag.

4. The method according to claim 1, wherein forming the first electrode comprises:

forming an electrical contact; and

forming a reflective electrode on the electrical contact.

34. The method according to claim 1, wherein the acoustic stress wave is generated by an expansion of plasma confined at the portion between the substrate and the semiconductor layer.

35. The method according to claim 1, wherein separating the substrate from the semiconductor layer comprises:

irradiating the portion between the substrate and the semiconductor layer with a laser beam;

generating plasma by melting the semiconductor layer at the portion, due to the irradiation of the laser beam; and

generating the acoustic stress wave by an expansion of the generated plasma.

36. The method according to claim 2, further comprising forming a passivation layer in the trench.

37. The method according to claim 36, wherein the passivation layer comprises at least one of SiO₂, SiN, epoxy-based photoresist, acrylic-based photoresist, SOG, and polyimide.

38. The method according to claim 36, wherein the passivation layer is partially disposed in the trench.

39. The method according to claim 36, wherein the passivation layer comprises:

a first passivation layer; and

a second passivation layer on the first passivation layer.

40. The method according to claim 36, wherein the passivation layer comprises an inorganic layer and/or an organic layer.

41. The method according to claim 2, wherein etching the chip separation region is performed before forming the first electrode.

42. The method according to claim 1, wherein the supporting layer has a thickness of 50 to 150 μ

m.

43. The method according to claim 1, wherein the supporting layer comprises a wafer or a metal.

44. The method according to claim 1, wherein separating the substrate from the semiconductor layer comprises irradiating a laser beam to the semiconductor layer through the substrate.

45. The method according to claim 44, wherein the laser beam has an energy density of more than 0.50 J/cm².

46. The method according to claim 44, wherein the laser beam has an energy density of 0.60 to 0.75 J/cm².

47. The method according to claim 1, further comprising forming a light extraction structure on the surface of the semiconductor layer.

48. The method according to claim 47, wherein forming the light extraction structure comprises forming the semiconductor layer on an irregular pattern of the substrate.

49. The method according to claim 47, wherein forming the light extraction structure comprises treating the surface of the semiconductor layer.

50. The method according to claim 49, wherein treating the surface comprises etching the surface of the semiconductor layer.

51. The method according to claim 1, further comprising dicing out into individual chips.

52. The method according to claim 51, wherein dicing out into individual chips comprises performing laser-scribing.

53. The method according to claim 1, further comprising forming a connection metal layer on the first electrode.

54. The method according to claim 53, wherein the connection metal layer comprises a reflective layer.

55. The method according to claim 53, wherein the connection metal layer has a multi-layer structure.

56. The method according to claim 53, wherein the connection metal layer comprises a bonding layer for attaching the supporting layer.

57. The method according to claim 53, wherein forming the connection metal layer comprises:

forming a first metal layer on the first electrode;

forming a diffusion barrier layer on the first metal layer; and

forming a second metal layer on the diffusion barrier layer.

58. The method according to claim 57, wherein the first metal layer comprises at least one of Ni, W, Ti, Pt, Au, Pd, Cu, Al, Cr, and Ag.

59. The method according to claim 57, wherein the diffusion barrier layer comprises at least one of Ni, W, Ti and Pt.

60. The method according to claim 57, wherein the second metal layer comprises at least one of Au and Cu.

61. The method according to claim 1, wherein the semiconductor layer comprises:

a p-type semiconductor layer;

an active layer on the p-type semiconductor layer; and

an n-type semiconductor layer on the active layer.

62. The method according to claim 61, wherein forming the semiconductor layer comprises forming a current diffusion layer on the p-type semiconductor layer.

63. The method according to claim 62, wherein the current diffusion layer comprises an InGaN layer or an InGaN/GaN superlattice layer.

64. The method according to claim 4, wherein a thickness of the reflective electrode is more than 100 Å

.

65. The method according to claim 4, wherein a thickness of the reflective electrode is equal to or less than 5000 Å

.

5-33. -33. (canceled)