SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR INTERFACING ONE OR MORE STORAGE DEVICES WITH A PLURALITY OF BRIDGE CHIPS

• US 20110004710A1
• Filed: 07/06/2009
• Published: 01/06/2011
• Est. Priority Date: 07/06/2009
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Danilak, Radoslav, Stenfort, Ross John
• Granted Patent: US 9,792,074 B2
• Time in Patent Office: Days
• US Class Current: 710/51
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0674 Disk device

Abstract

A system, method, and computer program product are provided for interfacing one or more storage devices with a plurality of bridge chips. One or more storage devices are provided. Additionally, a plurality of bridge chips are provided. Furthermore, at least one multiplexing device is provided for interfacing the one or more storage devices with the plurality of bridge chips.

Claims

1. An apparatus, comprising:

one or more storage devices;

a plurality of bridge chips; and

at least one multiplexing device for interfacing the one or more storage devices with the plurality of bridge chips.

2. The apparatus of claim 1, wherein the one or more storage devices include a Serial ATA (SATA) drive.

3. The apparatus of claim 1, wherein the at least one multiplexing device includes a multiplexer.

4. The apparatus of claim 1, wherein each of the plurality of bridge chips are capable of performing a protocol translation.

5. The apparatus of claim 1, wherein the at least one multiplexing device includes a plurality of ports.

6. The apparatus of claim 5, wherein the multiplexing device is configured such that each of the plurality of ports are active at the same time.

7. The apparatus of claim 6, wherein one of the plurality of bridge chips is connected to a group of the plurality of ports.

8. The apparatus of claim 1, wherein each of the plurality of bridge chips is dedicated to a single Serial Attached SCSI (SAS) port.

9. The apparatus of claim 1, further comprising a communication link between one or more of the plurality of bridge chips.

10. The apparatus of claim 9, wherein the communication link is configured such that the each of plurality of bridge chips are capable of communicating with each other of the plurality of bridge chips.

11. The apparatus of claim 10, wherein the communication link is configured to be utilized for error recovery.

12. The apparatus of claim 10, wherein the communication link is configured to be utilized for vender unique communication.

13. The apparatus of claim 1, wherein the at least one multiplexing device includes a plurality of input ports.

14. The apparatus of claim 13, wherein the input ports are connected to the storage device.

15. The apparatus of claim 14, wherein the multiplexing device includes a plurality of output ports.

16. The apparatus of claim 15, wherein the plurality of output ports are connected to the plurality of bridge chips.

17. The apparatus of claim 16, wherein a number of the plurality of output ports are divided equally and allocated to each of the plurality of bridge chips.

18. The apparatus of claim 1, wherein the at least one multiplexing device includes a bridge chip.

19. The apparatus of claim 1, wherein the at least one multiplexing device includes a bridge chip and a multiplexer.

20. A computer program product embodied on a computer readable medium, comprising:

computer code for sending a command from one of a plurality of bridge chips; and

computer code for receiving the command at one or more storage devices;

wherein the command is communicated utilizing at least one multiplexing device interfacing the one or more storage devices with the plurality of bridge chips.

21. A method, comprising:

sending a command from one of a plurality of bridge chips; and

receiving the command at one or more storage devices;

wherein the command is communicated utilizing at least one multiplexing device interfacing the one or more storage devices with the plurality of bridge chips.