Active Protection Device for Resistive Random Access Memory (RRAM) Formation

• US 20110007552A1
• Filed: 07/13/2009
• Published: 01/13/2011
• Est. Priority Date: 07/13/2009
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Huang, Shuiyuan, Manos, Peter Nicholas, Ahn, Yongchul, Khoury, Maroun, Khoueir, Antoine
• Granted Patent: US 7,965,538 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0059 Security or protection circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0083 Write to perform initialising, forming process, electro forming or conditioning
• CPC Class Codes: G11C 2213/78 Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

Apparatus and method for providing overcurrent protection to a resistive random access memory (RRAM) cell during an RRAM formation process used to prepare the cell for normal read and write operations. In accordance with various embodiments, the RRAM cell is connected between a first control line and a second control line, and an active protection device (APD) is connected between the second control line and an electrical ground terminal. A formation current is applied through the RRAM cell, and an activation voltage is concurrently applied to the APD to maintain a maximum magnitude of the formation current below a predetermined threshold level

Claims

1. An apparatus comprising:

a resistive random access memory (RRAM) cell connected between a first control line and a second control line; and

an active protection device (APD) connected between the second control line and an electrical ground terminal which, when activated, limits a maximum formation current magnitude applied to the RRAM cell during an RRAM formation process to prepare the RRAM cell for normal read and write operations.

2. The apparatus of claim 1, wherein the RRAM cell comprises a resistive sense element (RSE) connected in series with a switching device, wherein the RSE is connected to the first control line and the switching device is connected to the second control line.

3. The apparatus of claim 2, wherein the RSE comprises opposing electrode layers separated by an intervening barrier layer, wherein the RSE has a nominal first resistive state, and wherein migration of metal ions into the barrier layer during a programming operation transitions the RSE to a different, second resistive state.

4. The apparatus of claim 2, wherein the switching device is characterized as a metal oxide semiconductor field effect transistor (MOSFET), and wherein a third control line is connected to a gate region of the MOSFET to place the MOSFET in a drain-source conductive state.

5. The apparatus of claim 1, wherein the RRAM formation process flows current through the RRAM cell from the first control line to the second control line to prepare the RRAM cell for normal read and write operations.

6. The apparatus of claim 1, wherein the APD is characterized as a metal oxide semiconductor field effect transistor with a polysilicon gate region that spans an N+ doped source region and an N well drain region to provide electrical resistance responsive to application of a gate voltage to said gate to limit said current to said maximum magnitude.

7. The apparatus of claim 1, further comprising a plurality of RRAM cells connected between the first and second control lines, wherein the APD limits a maximum current magnitude applied to each of said plurality of RRAM cells during an RRAM formation process applied to said cells to prepare said cells for normal read and write operations.

8. The apparatus of claim 1, wherein the APD is further configured to be deactivated during subsequent storage of data to and reading of data from the RRAM cell.

9. The apparatus of claim 1, further comprising a third control line connected to the APD, wherein a first voltage is applied to the first control line during said RRAM formation process, and wherein a second voltage is concurrently applied to the third control line during said RRAM formation process greater than the first voltage.

10. The apparatus of claim 1, further comprising a secondary switching device connected in parallel with the APD between the second control line and the ground terminal, the secondary switching device actively connecting the second control line to said ground terminal.

11. A method comprising:

connecting a resistive random access memory (RRAM) cell between a first control line and a second control line, and an active protection device (APD) between the second control line and an electrical ground terminal; and

applying a formation current through the RRAM cell during an RRAM formation process to prepare the RRAM cell for normal read and write operations, and concurrently applying an activation voltage to the APD to maintain a maximum magnitude of said formation current below a predetermined threshold level.

12. The method of claim 11, wherein the applying step comprises applying a formation voltage to the first control line to flow said formation current through the RRAM cell from the first control line to the second control line, wherein the activation voltage is greater in magnitude than the formation voltage.

13. The method of claim 11, wherein the APD of the connecting step is characterized as a metal oxide semiconductor field effect transistor with a polysilicon gate region that spans an N+ doped source region and an N well drain region, and wherein the activation voltage concurrently applied to the APD is applied to said gate region to provide electrical resistance in series with the RRAM cell.

14. The method of claim 11, wherein the connecting step further comprises connecting a plurality of RRAM cells between the first and second control lines, and wherein the applying step comprises applying said formation current through each of said plurality of RRAM cells while concurrently activating the APD to limit the magnitude of the formation current below said threshold level.

15. The method of claim 11, further comprising a subsequent step of deactivating the APD during a read operation or a write operation upon the RRAM cell.

16. The method of claim 15, wherein the deactivating step comprises affirmatively connecting a gate terminal of the APD to the electrical ground terminal.

17. The method of claim 11, wherein the connecting step further comprises connecting a secondary switching device connected in parallel with the APD between the second control line and the ground terminal, and wherein the method further comprises subsequently actively connecting the second control line to said ground terminal.

18. The method of claim 11, wherein the RRAM cell of the connecting step comprises a resistive sense element (RSE) connected in series with a switching device, wherein the RSE is connected to the first control line and the switching device is connected to the second control line.

19. The method of claim 18, wherein the RSE comprises opposing electrode layers separated by an intervening barrier layer, wherein the RSE has a nominal first resistive state, and wherein migration of metal ions into the barrier layer during a programming operation transitions the RSE to a different, second resistive state.

20. The method of claim 18, wherein the switching device is characterized as a metal oxide semiconductor field effect transistor (MOSFET) with respective drain and source regions separated by an intervening channel region and spanned by a gate region, and wherein the applying step further comprises applying a voltage to the gate region to place the MOSFET in a drain-source conductive state to accommodate said flow of the formation current.