METHOD FOR EFFICIENT I/O CONTROLLER PROCESSOR INTERCONNECT COUPLING SUPPORTING PUSH-PULL DMA READ OPERATIONS
First Claim
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1. A system for I/O controller-processor interconnect coupling supporting push-pull DMA operations, comprising:
- a processor interconnect comprising a plurality of caches and memory subsystems;
an I/O controller coupled with the processor interconnect comprising;
a plurality of DMA read request queues;
a DMA read slot pool comprising a plurality of DMA read slots; and
an expander logic determining a priority of requests in said request queues.
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Abstract
A system for I/O controller-processor interconnect coupling supporting a push-pull DMA read operation, in one aspect, may comprise a processor interconnect comprising a plurality of caches and memory subsystems and an I/O controller coupled with the processor interconnect. The I/O controller may comprise a plurality of DMA read request queues, a DMA read slot pool comprising a plurality of DMA read slots, and an expander logic determining a priority of requests in said request queues.
10 Citations
15 Claims
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1. A system for I/O controller-processor interconnect coupling supporting push-pull DMA operations, comprising:
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a processor interconnect comprising a plurality of caches and memory subsystems; an I/O controller coupled with the processor interconnect comprising; a plurality of DMA read request queues; a DMA read slot pool comprising a plurality of DMA read slots; and an expander logic determining a priority of requests in said request queues. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of operations using an I/O controller-processor interconnect coupling, comprising:
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receiving a DMA read request; selecting a DMA read slot from a plurality to use as a scout slot; causing the scout slot to send a request to a processor interconnect to determine data origin of the DMA read request; prioritizing the DMA read request according to the determined data origin of the DMA read request; and allocating a slot of the plurality of slots in a DMA read slot pool according to the prioritizing. - View Dependent Claims (9, 10, 11)
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12. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method of operations using an I/O controller-processor interconnect coupling, comprising:
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receiving a DMA read request; selecting a DMA read slot from a plurality to use as a scout slot; causing the scout slot to send a request for a processor interconnect to determine data origin of the DMA read request; prioritizing the DMA read request according to the determined data origin of the DMA read request; and allocating a slot of the plurality of slots in a DMA read slot pool according to the prioritizing. - View Dependent Claims (13, 14, 15)
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Specification