SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20110012106A1
• Filed: 07/13/2010
• Published: 01/20/2011
• Est. Priority Date: 07/17/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: TERASHIMA, Mari, KUWABARA, Hideaki, MIYAKE, Hiroyuki, YAMAZAKI, Shunpei, SAKATA, Junichiro
• Granted Patent: US 8,378,343 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: G02F 2202/10 semiconductor
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A semiconductor device is provided in which a pixel portion and a driver circuit each including a thin film transistor are provided over one substrate; the thin film transistor in the pixel portion includes a gate electrode layer, a gate insulating layer, an oxide semiconductor layer having an end region with a small thickness, an oxide insulating layer in contact with part of the oxide semiconductor layer, source and drain electrode layers, and a pixel electrode layer; the thin film transistor in the pixel portion has a light-transmitting property; and source and drain electrode layers of the thin film transistor in the driver circuit portion are formed using a conductive material having lower resistance than a material of the source and drain electrode layer in the pixel portion.

Claims

1. A semiconductor device comprising:

a driver circuit comprising a first transistor and a pixel portion comprising a second transistor over a substrate;

the first transistor comprising;

a first gate electrode layer over the substrate;

a gate insulating layer over the first gate electrode layer;

a first oxide semiconductor layer comprising a first channel formation region over the first gate electrode layer with the gate insulating layer interposed therebetween;

a first source electrode layer and a first drain electrode layer over the first oxide semiconductor layer; and

an oxide insulating layer over the first source electrode layer and the first drain electrode layer;

the second transistor comprising;

a second gate electrode layer over the substrate;

the gate insulating layer over the second gate electrode layer;

a second oxide semiconductor layer over the second gate electrode layer with the gate insulating layer interposed therebetween;

a channel protective layer over the second gate electrode layer with the second oxide semiconductor layer interposed therebetween; and

a second source electrode layer and a second drain electrode layer over the second oxide semiconductor layer,

wherein the oxide insulating layer is in contact with the first channel formation region, and

wherein each of the second gate electrode layer, the gate insulating layer, the second oxide semiconductor layer, the channel protective layer, the second source electrode layer, and the second drain electrode layer has a light-transmitting property.

2. The semiconductor device according to claim 1, further comprising a pair of low-resistance drain regions between the first oxide semiconductor layer and each of the first source electrode layer and the first drain electrode layer.

3. The semiconductor device according to claim 1, further comprising:

an interlayer insulating film over the oxide insulating layer; and

a conductive layer over the first channel formation region with the interlayer insulating film interposed therebetween.

4. The semiconductor device according to claim 1, further comprising a pixel electrode layer electrically connected to one of the second source electrode layer and the second drain electrode layer.

5. The semiconductor device according to claim 1, wherein the first channel formation region is thinner than a region of the first oxide semiconductor layer which overlaps with one of the first source electrode layer and the first drain electrode layer.

6. The semiconductor device according to claim 1,

wherein an end portion of the first oxide semiconductor layer is positioned outer than a side surface of one of the first source electrode layer and the first drain electrode layer, and

wherein the end portion of the first oxide semiconductor layer is thinner than a region of the first oxide semiconductor layer which overlaps with one of the first source electrode layer and the first drain electrode layer.

7. The semiconductor device according to claim 2, wherein the pair of low-resistance drain regions, the second source electrode layer and the second drain electrode layer comprise the same material.

8. The semiconductor device according to claim 1, wherein the first source electrode layer and the first drain electrode layer comprise an element selected from Al, Cr, Cu, Ta, Ti, Mo and W as a main component or a stack of any of the above elements.

9. The semiconductor device according to claim 1, wherein the second source electrode layer and the second drain electrode layer comprise an indium oxide, an indium oxide-tin oxide alloy, an indium oxide-zinc oxide alloy, or zinc oxide.

10. The semiconductor device according to claim 1, further comprising:

a capacitor portion over the substrate,

wherein the capacitor portion comprises a capacitor wiring and a capacitor electrode overlapping with the capacitor wiring, and

wherein each of the capacitor wiring and the capacitor electrode has a light-transmitting property.

11. The semiconductor device according to claim 1, further comprising:

a protective insulating film over the oxide insulating layer, the second source electrode layer and the second drain electrode layer,

wherein the protective insulating film is provided so as to be in contact with the gate insulating layer.

12. The semiconductor device according to claim 1, wherein the second oxide semiconductor layer comprises a pair of second high-resistance drain regions and a second channel formation region provided between the pair of second high-resistance drain regions.

13. A semiconductor device comprising:

a driver circuit comprising a first transistor and a pixel portion comprising a second transistor over a substrate;

the first transistor comprising;

a first gate electrode layer over the substrate;

a gate insulating layer over the first gate electrode layer;

a first oxide semiconductor layer over the first gate electrode layer with the gate insulating layer interposed therebetween;

a first source electrode layer and a first drain electrode layer over the first oxide semiconductor layer; and

an oxide insulating layer over the first source electrode layer and the first drain electrode layer;

the second transistor comprising;

a second gate electrode layer over the substrate;

the gate insulating layer over the second gate electrode layer;

a second oxide semiconductor layer over the second gate electrode layer with the gate insulating layer interposed therebetween;

a channel protective layer over the second gate electrode layer with the second oxide semiconductor layer interposed therebetween; and

a second source electrode layer and a second drain electrode layer over the second oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises a pair of first high-resistance drain regions and a first channel formation region provided between the pair of first high-resistance drain regions,

wherein the oxide insulating layer is in contact with the first channel formation region, and

wherein each of the second gate electrode layer, the gate insulating layer, the second oxide semiconductor layer, the channel protective layer, the second source electrode layer, and the second drain electrode layer has a light-transmitting property.

14. The semiconductor device according to claim 13, further comprising a pair of low-resistance drain regions between the first oxide semiconductor layer and each of the first source electrode layer and the first drain electrode layer.

15. The semiconductor device according to claim 13, further comprising:

an interlayer insulating film over the oxide insulating layer; and

a conductive layer over the first channel formation region with the interlayer insulating film interposed therebetween.

16. The semiconductor device according to claim 13, further comprising a pixel electrode layer electrically connected to one of the second source electrode layer and the second drain electrode layer.

17. The semiconductor device according to claim 13, wherein the first channel formation region is thinner than a region of the first oxide semiconductor layer which overlaps with one of the first source electrode layer and the first drain electrode layer.

18. The semiconductor device according to claim 13,

wherein an end portion of the first oxide semiconductor layer is positioned outer than a side surface of one of the first source electrode layer and the first drain electrode layer, and

wherein the end portion of the first oxide semiconductor layer is thinner than a region of the first oxide semiconductor layer which overlaps with one of the first source electrode layer and the first drain electrode layer.

19. The semiconductor device according to claim 14, wherein the pair of low-resistance drain regions, the second source electrode layer and the second drain electrode layer comprise the same material.

20. The semiconductor device according to claim 13, wherein the first source electrode layer and the first drain electrode layer comprise an element selected from Al, Cr, Cu, Ta, Ti, Mo and W as a main component or a stack of any of the above elements.

21. The semiconductor device according to claim 13, wherein the second source electrode layer and the second drain electrode layer comprise an indium oxide, an indium oxide-tin oxide alloy, an indium oxide-zinc oxide alloy, or a zinc oxide.

22. The semiconductor device according to claim 13, further comprising:

a capacitor portion over the substrate,

wherein the capacitor portion comprises a capacitor wiring and a capacitor electrode overlapping with the capacitor wiring, and

wherein each of the capacitor wiring and the capacitor electrode has a light-transmitting property.

23. The semiconductor device according to claim 13, further comprising:

a protective insulating film over the oxide insulating layer, the second source electrode layer and the second drain electrode layer,

wherein the protective insulating film is provided so as to be in contact with the gate insulating layer.

24. The semiconductor device according to claim 13, wherein the second oxide semiconductor layer comprises a pair of second high-resistance drain regions and a second channel formation region provided between the pair of second high-resistance drain regions.

25. A method for manufacturing a semiconductor device comprising:

forming a first gate electrode layer and a second gate electrode layer over a substrate;

forming a gate insulating layer over the first gate electrode layer and the second gate electrode layer;

forming an oxide semiconductor film over the gate insulating layer;

performing first heat treatment in order to decrease a hydrogen concentration in the oxide semiconductor film;

forming an oxide conductive film over the oxide semiconductor film after performing the first heat treatment;

forming a first conductive film over the oxide conductive film;

patterning the oxide semiconductor film, the oxide conductive film and the first conductive film to form a first oxide semiconductor layer over the first gate electrode layer with the gate insulating layer interposed therebetween, a second oxide semiconductor layer over the second gate electrode layer with the gate insulating layer interposed therebetween, a pair of low-resistance drain regions over the first oxide semiconductor layer, a first source electrode layer and a first drain electrode layer over the pair of low-resistance drain regions;

forming an oxide insulating layer over the first source electrode layer, the first drain electrode layer, and the second oxide semiconductor layer so as to be in contact with the second oxide semiconductor layer and a first channel formation region of the first oxide semiconductor layer which is provided between the first source electrode layer and the first drain electrode layer;

performing second heat treatment after forming the oxide insulating layer;

forming a channel protective layer over the second gate electrode layer with the second oxide semiconductor layer interposed therebetween by patterning the oxide insulating layer after performing the second heat treatment; and

forming a second source electrode layer and a second drain electrode layer over the second oxide semiconductor layer so that each of the second source electrode layer and the second drain electrode layer partly overlaps with the channel protective layer.

26. The method for manufacturing a semiconductor device according to claim 25, wherein the first source electrode layer and the first drain electrode layer comprise an element selected from Al, Cr. Cu, Ta, Ti, Mo, and W as a main component or a stack of any of the above elements.

27. The method for manufacturing a semiconductor device according to claim 25, wherein the second source electrode layer and the second drain electrode layer comprise an indium oxide, an indium oxide-tin oxide alloy, an indium oxide-zinc oxide alloy, or a zinc oxide.

28. The method for manufacturing a semiconductor device according to claim 25, wherein the first heat treatment is performed in an inert gas atmosphere or under a reduced pressure.

29. The method for manufacturing a semiconductor device according to claim 25, wherein the first oxide semiconductor layer is formed so that the first channel formation region is thinner than a region of the first oxide semiconductor layer which overlaps with one of the first source electrode layer and the first drain electrode layer.

30. The method for manufacturing a semiconductor device according to claim 25, further comprising:

forming an interlayer insulating film over the oxide insulating layer, the second source electrode layer and the second drain electrode layer;

forming a second conductive film over the interlayer insulating film; and

patterning the second conductive film to form a conductive layer and a pixel electrode layer,

wherein the conductive layer is formed so as to overlap with the first channel formation region, and

wherein the pixel electrode layer is formed so as to be electrically connected to one of the second source electrode layer and the second drain electrode layer.

31. The method for manufacturing a semiconductor device according to claim 25, further comprising forming a protective insulating layer over the oxide insulating layer, the second source electrode layer and the second drain electrode layer so as to be in contact with the gate insulating layer.

32. The method for manufacturing a semiconductor device according to claim 25, wherein the first oxide semiconductor layer is formed so that an end portion of the first oxide semiconductor layer is provided outer than a side surface of one of the first source electrode layer and the first drain electrode layer and thinner than a region of the first oxide semiconductor layer which overlaps with one of the first source electrode layer and the first drain electrode layer.

33. The method for manufacturing a semiconductor device according to claim 25, further comprising performing third heat treatment after forming the channel protective layer.

34. A method for manufacturing a semiconductor device comprising:

forming a first gate electrode layer and a second gate electrode layer over a substrate;

forming a gate insulating layer over the first gate electrode layer and the second gate electrode layer;

forming an oxide semiconductor film over the gate insulating layer;

performing first heat treatment in order to decrease a hydrogen concentration in the oxide semiconductor film;

performing second heat treatment for the oxide semiconductor film after performing the first heat treatment;

forming an oxide conductive film over the oxide semiconductor film after performing the second heat treatment;

forming a first conductive film over the oxide conductive film;

patterning the oxide semiconductor film, the oxide conductive film, and the first conductive film to form a first oxide semiconductor layer over the first gate electrode layer with the gate insulating layer interposed therebetween, a second oxide semiconductor layer over the second gate electrode layer with the gate insulating layer interposed therebetween, a pair of low-resistance drain regions over the first oxide semiconductor layer, a first source electrode layer and a first drain electrode layer over the pair of low-resistance drain regions;

forming an oxide insulating layer so as to be in contact with the second oxide semiconductor layer and a first channel formation region of the first oxide semiconductor layer which is provided between the first source electrode layer and the first drain electrode layer;

performing third heat treatment after forming the oxide insulating layer;

forming a channel protective layer over the second gate electrode layer with the second oxide semiconductor layer interposed therebetween by patterning the oxide insulating layer after performing the third heat treatment; and

forming a second source electrode layer and a second drain electrode layer over the second oxide semiconductor layer so that each of the second source electrode layer and the second drain electrode layer partly overlaps with the channel protective layer,

wherein the second heat treatment is performed in an oxygen atmosphere, an N₂O gas atmosphere or ultra-dry air.

35. The method for manufacturing a semiconductor device according to claim 34, wherein the first source electrode layer and the first drain electrode layer comprise an element selected from Al, Cr. Cu, Ta, Ti, Mo, and W as a main component or a stack of any of the above elements.

36. The method for manufacturing a semiconductor device according to claim 34, wherein the second source electrode layer and the second drain electrode layer comprise an indium oxide, an indium oxide-tin oxide alloy, an indium oxide-zinc oxide alloy, or a zinc oxide.

37. The method for manufacturing a semiconductor device according to claim 34, wherein the first heat treatment is performed in an inert gas atmosphere or under a reduced pressure.

38. The method for manufacturing a semiconductor device according to claim 34, wherein the first oxide semiconductor layer is formed so that the first channel formation region is thinner than a region of the first oxide semiconductor layer which overlaps with one of the first source electrode layer and the first drain electrode layer.

39. The method for manufacturing a semiconductor device according to claim 34, further comprising:

forming an interlayer insulating film over the oxide insulating layer, the second source electrode layer and the second drain electrode layer;

forming a second conductive film over the interlayer insulating film; and

patterning the second conductive film to form a conductive layer and a pixel electrode layer,

wherein the conductive layer is formed so as to overlap with the first channel formation region, and

wherein the pixel electrode layer is formed so as to be electrically connected to one of the second source electrode layer and the second drain electrode layer.

40. The method for manufacturing a semiconductor device according to claim 34, further comprising forming a protective insulating layer over the oxide insulating layer, the second source electrode layer and the second drain electrode layer so as to be in contact with the gate insulating layer.

41. The method for manufacturing a semiconductor device according to claim 34, wherein the first oxide semiconductor layer is formed so that an end portion of the first oxide semiconductor layer is provided outer than a side surface of one of the first source electrode layer and the first drain electrode layer and thinner than a region of the first oxide semiconductor layer which overlaps with one of the first source electrode layer and the first drain electrode layer.

42. The method for manufacturing a semiconductor device according to claim 34, further comprising performing fourth heat treatment after forming the channel protective layer.