Method and System for Determining Synchronization Status in a Wide Band CDMA Network

• US 20110019727A1
• Filed: 10/05/2010
• Published: 01/27/2011
• Est. Priority Date: 02/15/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Landau, Uri M., Catreux-Erceg, Severine, Kent, Mark, Erceg, Vinko
• Granted Patent: US 8,626,226 B2
• Time in Patent Office: Days
• US Class Current: 375/227
• CPC Class Codes: H04W 52/241 taking into account channel quality metrics, e.g. SIR, SNR, CIR, Eb/lo
• CPC Class Codes: H04W 52/44 in connection with interruption of transmission
• CPC Class Codes: H04W 52/56 Detection of errors of TPC bits

Abstract

A method and system for determining synchronization status in a wide band CDMA (WCDMA) network may comprise calculating a signal to noise ratio (SNR) of a downlink dedicated physical channel (DPCH) based on a plurality of transmit power control (TPC) bits received via the downlink dedicated physical channel (DPCH), wherein the value of at least one of the plurality of TPC bits is not known when at least one of the plurality of TPC bits is received. The transmit circuitry may be controlled based on the calculated signal to noise ratio. The transmit circuitry may be disabled if the calculated SNR of the plurality of TPC bits is below a first channel threshold. The transmit circuitry may be enabled if the calculated SNR of the plurality of TPC bits is above a second channel threshold.

Claims

1. A method for signal processing, the method comprising:

calculating a signal to noise ratio (SNR) of a downlink dedicated physical channel (DPCH) based on a plurality of transmit power control (TPC) bits received via said DPCH, wherein a value of at least one of said received plurality of TPC bits is not known.

2. The method according to claim 1, comprising controlling transmit circuitry based on said calculated SNR.

3. The method according to claim 1, comprising disabling transmit circuitry, if said calculated SNR of said plurality of TPC bits is below a first channel threshold.

4. The method according to claim 1, comprising enabling transmit circuitry, if said calculated SNR of said plurality of TPC bits is above a second channel threshold.

5. The method according to claim 1, comprising summing portions of said plurality of TPC bits that are received via a plurality of multipaths over said DPCH to generate an in-phase (I) component and a quadrature (Q) component.

6. The method according to claim 5, comprising:

summing said generated I component and said generated Q component to determine signal power of said DPCH; and

squaring said summed said generated I component and said generated Q component to determine said signal power of said DPCH.

7. The method according to claim 6, comprising calculating a norm of said squared said summed said generated I component and said generated Q component by dividing said squared said summed said generated I component and said generated Q component by a number of said plurality of TPC bits per slot of said DPCH to determine said signal power of said DPCH.

8. The method according to claim 7, comprising averaging said norm of said squared said summed said generated I component and said generated Q component over a time window.

9. The method according to claim 5, comprising subtracting said generated I component and said generated Q component to determine noise power of said DPCH.

10. The method according to claim 9, comprising:

squaring said subtracted said generated I component and said generated Q component to determine said noise power of said DPCH; and

summing said squared said subtracted said generated I component and said generated Q component over a plurality of TPC symbols to determine said noise power of said DPCH.

11. The method according to claim 10, wherein said plurality of TPC symbols is half of said plurality of TPC bits per slot of said DPCH.

12. The method according to claim 10, comprising:

calculating a norm of said summed said squared said subtracted said generated I component and said generated Q component by dividing said summed said squared said subtracted said generated I component and said generated Q component by a number of said plurality of TPC bits per slot of said DPCH to determine said noise power of said DPCH; and

averaging said norm of said summed said squared said subtracted said generated I component and said generated Q component over a time window to determine a noise power estimate of said DPCH.

13. The method according to claim 1, comprising calculating said SNR of said DPCH for a plurality of multipaths by averaging a calculated SNR of each of a plurality of radio link sets.

14. The method according to claim 13, comprising calculating said SNR of said DPCH for each of said plurality of radio link sets to determine a plurality of signal to noise ratios (SNRs).

15. The method according to claim 14, comprising enabling transmit circuitry, if and only if at least one of said plurality of SNRs is above a first channel threshold.

16. A system for signal processing, the system comprising:

one or more circuits that are operable to calculate a signal to noise ratio (SNR) of a downlink dedicated physical channel (DPCH) based on a plurality of transmit power control (TPC) bits received via said DPCH, wherein a value of at least one of said received plurality of TPC bits is not known.

17. The system according to claim 16, wherein said one or more circuits are operable to control transmit circuitry based on said calculated SNR.

18. The system according to claim 16, wherein said one or more circuits are operable to disable transmit circuitry, if said calculated SNR of said plurality of TPC bits is below a first channel threshold.

19. The system according to claim 16, wherein said one or more circuits are operable to enable transmit circuitry, if said calculated SNR of said plurality of TPC bits is above a second channel threshold.

20. The system according to claim 16, wherein said one or more circuits are operable to sum portions of said plurality of TPC bits that are received via a plurality of multipaths over said DPCH to generate an in-phase (I) component and a quadrature (Q) component.

21. The system according to claim 20, wherein said one or more circuits are operable to:

sum said generated I component and said generated Q component to determine signal power of said DPCH; and

square said summed said generated I component and said generated Q component to determine said signal power of said DPCH.

22. The system according to claim 21, wherein said one or more circuits are operable to calculate a norm of said squared said summed said generated I component and said generated Q component by dividing said squared said summed said generated I component and said generated Q component by a number of said plurality of TPC bits per slot of said DPCH to determine said signal power of said DPCH.

23. The system according to claim 22, wherein said one or more circuits are operable to average said norm of said squared said summed said generated I component and said generated Q component over a time window.

24. The system according to claim 20, wherein said one or more circuits are operable to subtract said generated I component and said generated Q component to determine noise power of said DPCH.

25. The system according to claim 24, wherein said one or more circuits are operable to:

square said subtracted said generated I component and said generated Q component to determine said noise power of said DPCH; and

sum said squared said subtracted said generated I component and said generated Q component over a plurality of TPC symbols to determine said noise power of said DPCH.

26. The system according to claim 25, wherein said plurality of TPC symbols is half of said plurality of TPC bits per slot of said DPCH.

27. The system according to claim 25, wherein said one or more circuits are operable to:

calculate a norm of said summed said squared said subtracted said generated I component and said generated Q component by dividing said summed said squared said subtracted said generated I component and said generated Q component by a number of said plurality of TPC bits per slot of said DPCH to determine said noise power of said DPCH; and

average said norm of said summed said squared said subtracted said generated I component and said generated Q component over a time window.

28. The system according to claim 16, wherein said one or more circuits are operable to calculate said SNR of said DPCH for a plurality of multipaths by averaging a calculated SNR of each of a plurality of radio link sets.

29. The system according to claim 28, wherein said one or more circuits are operable to calculate said SNR of said DPCH for each of said plurality of radio link sets to determine a plurality of signal to noise ratios (SNRs).

30. The system according to claim 29, wherein said one or more circuits are operable to enable transmit circuitry if and only if at least one of said plurality of SNRs is above a first channel threshold.