SELF-TIMED WRITE BOOST FOR SRAM CELL WITH SELF MODE CONTROL

• US 20110026309A1
• Filed: 09/30/2009
• Published: 02/03/2011
• Est. Priority Date: 08/03/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Inventors: Batra, Naveen, KUMAR, Ashish
• Granted Patent: US 8,259,486 B2
• Time in Patent Office: Days
• US Class Current: 365/154
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence

Abstract

A write boost circuit provides an automatic mode control for boost with different modalities with respect to the external supply voltage and also with respect to the extent of boost required at different process corners. The write boost circuit also takes care of the minimum boost provided to process corners with good writability where less boost is required. The boost is realized in terms of ground raising in the particular context and in general applicable to all other methods.

Claims

1. A write boost circuit for an SRAM cell comprising:

an input terminal for coupling to a power terminal of an SRAM cell;

a diode coupled between the input terminal and ground;

a first transistor coupled between the input terminal and a source of supply voltage; and

a second transistor coupled between the input terminal and ground.

2. The write boost circuit of claim 1 wherein the diode comprises an N-channel diode-connected transistor.

3. The write boost circuit of claim 1 wherein a gate of the first transistor receives a boost control signal.

4. The write boost circuit of claim 1 wherein a gate of the second transistor receives a ground control signal.

5. The write boost circuit of claim 1 wherein the first transistor comprises an N-channel transistor.

6. The write boost circuit of claim 1 wherein the second transistor comprises an N-channel transistor.

7. The write boost circuit of claim 1 further comprising a diode interposed between the first transistor and the source of supply voltage.

8. The write boost circuit of claim 7 wherein the diode comprises a P-channel diode-connected transistor.

9. A write boost circuit for an SRAM cell comprising:

an input terminal for coupling to a power terminal of an SRAM cell;

a diode coupled between the input terminal and ground;

a first write boost path coupled between the input terminal and a source of supply voltage;

a second write boost path coupled between the input terminal and a source of supply voltage; and

a transistor coupled between the input terminal and ground.

10. The write boost circuit of claim 9 wherein the diode comprises an N-channel diode-connected transistor.

11. The write boost circuit of claim 9 wherein the first and second write boost paths are differently sized.

12. The write boost circuit of claim 9 wherein the first write boost path comprises a first transistor, a second transistor, and a diode serially coupled between the input terminal and a source of supply voltage.

13. The write boost circuit of claim 12 wherein the first transistor comprises an N-channel transistor for receiving a boost control signal, and the second transistor comprises a P-channel transistor for receiving an additional control signal.

14. The write boost circuit of claim 9 wherein the second write boost path comprises a first transistor, a second transistor, and a diode serially coupled between the input terminal and a source of supply voltage.

15. The write boost circuit of claim 14 wherein the first transistor comprises an N-channel transistor for receiving a boost control signal, and the second transistor comprises a P-channel transistor for receiving an additional control signal.

16. The write boost circuit of claim 9 wherein the first and second write boost paths are coupled to a power-on reset circuit.

17. The write boost circuit of claim 16 wherein the first write boost path further comprises an inverter having an input coupled to the power-on reset circuit.

18. The write boost circuit of claim 16 wherein the second write boost path further comprises an inverter having an input coupled to the power-on reset circuit.

19. The write boost circuit of claim 9 wherein the first write boost path is coupled to a first output of a power-on reset circuit.

20. The write boost circuit of claim 9 wherein the second write boost path is coupled to a second output of a power-on reset circuit.