SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20110032444A1
• Filed: 08/02/2010
• Published: 02/10/2011
• Est. Priority Date: 08/07/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: OIKAWA, Yoshiaki, MARUYAMA, Hotaka, OKAZAKI, Kenichi, TSUBUKU, Masashi, YAMAZAKI, Shunpei, SAKAKURA, Masayuki, SAKATA, Junichiro
• Granted Patent: US 8,654,272 B2
• Time in Patent Office: Days
• US Class Current: 349/42
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G02F 1/133302 Rigid substrates, e.g. inorganic substrates
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/133357 Planarisation layers
• CPC Class Codes: G02F 1/133528 Polarisers
• CPC Class Codes: G02F 1/1337 Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/13394 spacers regularly patterned on the cell subtrate, e.g. walls, pillars G02F1/133377 takes precedence
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 : employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/247 : Amorphous materials
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78648 : arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78693 : the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is sandwiched between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected to each other in an opening provided in a gate insulating film through an oxide conductive layer.

Claims

1. A semiconductor device comprising:

a substrate;

a driver circuit portion including a first transistor over the substrate; and

a pixel portion including a second transistor and a pixel electrode layer over the substrate,

wherein the first transistor comprises

a first electrode layer;

a first insulating layer over the first electrode layer;

a first oxide semiconductor layer over the first insulating layer;

a second electrode layer and a third electrode layer over the first oxide semiconductor layer;

a second insulating layer over the second electrode layer, the third electrode layer, and the first oxide semiconductor layer, wherein the second insulating layer is in contact with the first oxide semiconductor layer; and

a conductive layer over the second insulating layer, wherein the conductive layer and the first electrode layer are overlapped with each other with the first insulating layer, the first oxide semiconductor layer, and the second insulating layer interposed therebetween,

wherein the second transistor comprises;

a fourth electrode layer;

the first insulating layer over the fourth electrode layer;

a second oxide semiconductor layer over the first insulating layer;

a fifth electrode layer and a sixth electrode layer over the second oxide semiconductor layer; and

the second insulating layer over the fifth electrode layer, the sixth electrode layer, and the second oxide semiconductor layer, the second insulating layer being in contact with the second oxide semiconductor layer, and

wherein the pixel electrode layer is electrically connected to the second transistor.

2. The semiconductor device according to claim 1,

wherein the first transistor further comprises a first oxide conductive layer and the second transistor further comprises a second oxide conductive layer,

wherein the first oxide conductive layer is interposed between the first oxide semiconductor layer and the second electrode layer, and

wherein the second oxide conductive layer is interposed between the second oxide semiconductor layer and the fifth electrode layer.

3. The semiconductor device according to claim 2,

wherein each the first oxide conductive layer and the second oxide conductive layer includes any one of zinc oxide, aluminum zinc oxide, aluminum zinc oxynitride, and gallium zinc oxide.

4. The semiconductor device according to claim 1,

wherein the first insulating layer is formed using a single layer or stacked layers of a silicon oxide layer, a silicon oxynitride layer, or an aluminum oxide layer.

5. The semiconductor device according to claim 1,

wherein the pixel electrode layer and the conductive layer are formed using the same material which is any one of indium oxide, an indium oxide-tin oxide alloy, an indium oxide-zinc oxide alloy, and zinc oxide.

6. The semiconductor device according to claim 1,

wherein the first oxide semiconductor layer is formed using the same material as that of the second oxide semiconductor layer,

wherein the first electrode layer is formed using the same material as that of the fourth electrode layer, and

wherein the second electrode layer comprises the same layered structure as that of the third electrode layer, the fifth electrode layer, and the sixth electrode layer.

7. The semiconductor device according to claim 1,

wherein each the first oxide semiconductor layer and the second oxide semiconductor layer comprises a channel formation region, a source region, and a drain region, and

wherein a carrier concentration of the channel formation region is lower than that of the source region and the drain region.

8. A semiconductor device comprising:

a substrate;

a driver circuit portion including a first transistor over the substrate;

a pixel portion including a second transistor and a pixel electrode layer over the substrate; and

a first wiring and a second wiring,

wherein the first transistor comprises;

a first electrode layer;

a first insulating layer over the first electrode layer;

a first oxide semiconductor layer over the first insulating layer;

a second electrode layer and a third electrode layer over the first oxide semiconductor layer;

a second insulating layer over the second electrode layer, the third electrode layer, and the first oxide semiconductor layer, wherein the second insulating layer is in contact with the first oxide semiconductor layer; and

a conductive layer over the second insulating layer, wherein the conductive layer and the first electrode layer are overlapped with each other with the first insulating layer, the first oxide semiconductor layer, and the second insulating layer interposed therebetween,

wherein the second transistor comprises;

a fourth electrode layer;

the first insulating layer over the fourth electrode layer;

a second oxide semiconductor layer over the first insulating layer;

a fifth electrode layer and a sixth electrode layer over the second oxide semiconductor layer; and

the second insulating layer over the fifth electrode layer, the sixth electrode layer, and the second oxide semiconductor layer, the second insulating layer being in contact with the second oxide semiconductor layer,

wherein the first wiring is formed using the same material as that of the first electrode layer and the fourth electrode layer,

wherein the second wiring comprises the same layered structure as that of the second electrode layer, the third electrode layer, the fifth electrode layer, and the sixth electrode layer, and

wherein the pixel electrode layer is electrically connected to the second transistor.

9. The semiconductor device according to claim 8,

wherein the first transistor further comprises a first oxide conductive layer and the second transistor further comprises a second oxide conductive layer,

wherein the first oxide conductive layer is interposed between the first oxide semiconductor layer and the second electrode layer, and

wherein the second oxide conductive layer is interposed between the second oxide semiconductor layer and the fifth electrode layer.

10. The semiconductor device according to claim 9,

wherein each the first oxide conductive layer and the second oxide conductive layer includes any one of zinc oxide, aluminum zinc oxide, aluminum zinc oxynitride, and gallium zinc oxide.

11. The semiconductor device according to claim 8,

wherein the first insulating layer is formed using a single layer or stacked layers of a silicon oxide layer, a silicon oxynitride layer, or an aluminum oxide layer.

12. The semiconductor device according to claim 8,

wherein the pixel electrode layer and the conductive layer are formed using the same material which is any one of indium oxide, an indium oxide-tin oxide alloy, an indium oxide-zinc oxide alloy, and zinc oxide.

13. The semiconductor device according to claim 8,

wherein the first oxide semiconductor layer is formed using the same material as that of the second oxide semiconductor layer.

14. The semiconductor device according to claim 8,

wherein each the first oxide semiconductor layer and the second oxide semiconductor layer comprises a channel formation region, a source region, and a drain region, and

wherein a carrier concentration of the channel formation region is lower than that of the source region and the drain region.

15. The semiconductor device according to claim 8,

wherein the first wiring is electrically connected to the second wiring through an opening provided in the first insulating layer over the first wiring.

16. A semiconductor device comprising:

a substrate;

a driver circuit portion including a first transistor over the substrate;

a pixel portion including a second transistor and a pixel electrode layer over the substrate;

a first alignment film over the pixel electrode layer; and

a liquid crystal layer over the first alignment film,

wherein the first transistor comprises;

a first electrode layer;

a first insulating layer over the first electrode layer;

a first oxide semiconductor layer over the first insulating layer;

a second electrode layer and a third electrode layer over the first oxide semiconductor layer;

a second insulating layer over the second electrode layer, the third electrode layer, and the first oxide semiconductor layer, wherein the second insulating layer is in contact with the first oxide semiconductor layer; and

a conductive layer over the second insulating layer, wherein the conductive layer and the first electrode layer are overlapped with each other with the first insulating layer, the first oxide semiconductor layer, and the second insulating layer interposed therebetween,

wherein the second transistor comprises;

a fourth electrode layer;

the first insulating layer over the fourth electrode layer;

a second oxide semiconductor layer over the first insulating layer;

a fifth electrode layer and a sixth electrode layer over the second oxide semiconductor layer; and

the second insulating layer over the fifth electrode layer, the sixth electrode layer, and the second oxide semiconductor layer, the second insulating layer being in contact with the second oxide semiconductor layer, and

wherein the pixel electrode layer is electrically connected to the second transistor.

17. The semiconductor device according to claim 16,

wherein the first transistor further comprises a first oxide conductive layer and the second transistor further comprises a second oxide conductive layer,

wherein the first oxide conductive layer is interposed between the first oxide semiconductor layer and the second electrode layer, and

wherein the second oxide conductive layer is interposed between the second oxide semiconductor layer and the fifth electrode layer.

18. The semiconductor device according to claim 17,

wherein each the first oxide conductive layer and the second oxide conductive layer includes any one of zinc oxide, aluminum zinc oxide, aluminum zinc oxynitride, and gallium zinc oxide.

19. The semiconductor device according to claim 16,

wherein the first insulating layer is formed using a single layer or stacked layers of a silicon oxide layer, a silicon oxynitride layer, or an aluminum oxide layer.

20. The semiconductor device according to claim 16,

wherein the pixel electrode layer and the conductive layer are formed using the same material which is any one of indium oxide, an indium oxide-tin oxide alloy, an indium oxide-zinc oxide alloy, and zinc oxide.

21. The semiconductor device according to claim 16,

wherein the first oxide semiconductor layer is formed using the same material as that of the second oxide semiconductor layer,

wherein the first electrode layer is formed using the same material as that of the fourth electrode layer, and

wherein the second electrode layer comprises the same layered structure as that of the third electrode layer, the fifth electrode layer, and the sixth electrode layer.

22. The semiconductor device according to claim 16,

wherein each the first oxide semiconductor layer and the second oxide semiconductor layer comprises a channel formation region, a source region, and a drain region, and

wherein a carrier concentration of the channel formation region is lower than that of the source region and the drain region.

23. The semiconductor device according to claim 16, further comprising a counter substrate, a second alignment film, and a counter electrode interposed between the counter substrate and the second alignment film,

wherein the liquid crystal layer is interposed between the first alignment film and the second alignment film.

24. A manufacturing method of a semiconductor device, comprising the steps of:

forming a first gate electrode in a driver circuit portion and a second gate electrode in a pixel portion, over a substrate;

forming a gate insulating film over the first gate electrode and the second gate electrode;

forming a first oxide semiconductor layer and a second oxide semiconductor layer over the gate insulating film;

performing a first heat treatment for dehydration or dehydrogenation;

forming first source and drain electrodes over the first oxide semiconductor layer and second source and drain electrodes over the second oxide semiconductor layer;

forming an insulating film over the first oxide semiconductor layer, the second oxide semiconductor layer, the first source and drain electrodes and the second source and drain electrodes;

forming a conductive layer and a pixel electrode over the insulating film; and

performing a second heat treatment under air atmosphere after forming the insulating film,

wherein the first gate electrode is overlapped with the first oxide semiconductor layer and the second gate electrode is overlapped with the second oxide semiconductor layer,

wherein the conductive layer is overlapped with the first gate electrode and the first oxide semiconductor layer, and

wherein the pixel electrode is formed in the pixel portion.

25. The manufacturing method of a semiconductor device according to claim 24, further comprising the step of forming a first oxide conductive layer and a second conductive layer,

wherein the first oxide conductive layer is interposed between the first oxide semiconductor layer and the first drain electrode, and

wherein the second conductive layer is interposed between the second oxide semiconductor layer and the second drain electrode.

26. The manufacturing method of a semiconductor device according to claim 24,

wherein the pixel electrode and the conductive layer are formed using the same material which is any one of indium oxide, an indium oxide-tin oxide alloy, an indium oxide-zinc oxide alloy, and zinc oxide.

27. The manufacturing method of a semiconductor device according to claim 24,

wherein each the first oxide semiconductor layer and the second oxide semiconductor layer comprises a channel formation region, a source region, and a drain region, and

wherein a carrier concentration of the channel formation region is lower than that of the source region and the drain region.