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CONTROLLER AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

  • US 20110038212A1
  • Filed: 03/02/2010
  • Published: 02/17/2011
  • Est. Priority Date: 08/13/2009
  • Status: Active Grant
First Claim
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1. A controller comprising:

  • a program interface configured to set a first threshold voltage level according to writing data in memory cells;

    a generation unit configured to aggregate comparison results between second threshold voltage levels held in the memory cells and predetermined third threshold voltage levels, and generate a histogram of the second threshold voltage levels;

    an estimation unit configured to estimate statistical parameter of a distribution of the second threshold voltage levels with respect to the first threshold voltage level based on the histogram;

    a determination unit configured to determine a fifth threshold voltage level defining a boundary of a fourth threshold voltage level indicating a read result of the memory cells from the third threshold voltage levels based on the statistical parameter in such a manner that mutual information amount between the first threshold voltage level and the fourth threshold voltage level becomes maximum; and

    a read interface configured to cause each of the memory cells to compare the second threshold voltage level with the fifth threshold voltage level, and obtain the fourth threshold voltage level according to a comparison result.

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