BATTERY BACKUP SYSTEM WITH SLEEP MODE

• US 20110043043A1
• Filed: 11/02/2010
• Published: 02/24/2011
• Est. Priority Date: 05/22/2008
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Marshall, Brad D., Skinner, R. Brian, Anupindi, Lakshmana M.
• Granted Patent: US 8,030,897 B2
• Time in Patent Office: Days
• US Class Current: 307/66
• CPC Class Codes: H01M 10/425 Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing printed circuits H05K1/00
• CPC Class Codes: H01M 10/44 Methods for charging or discharging circuits for charging H02J7/00
• CPC Class Codes: H01M 10/48 Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte constructional details of current conducting connections for detecting conditions inside cells or batteries, e.g. details of voltage sensing terminals, H01M50/569
• CPC Class Codes: H01M 2010/4271 Battery management systems including electronic circuits, e.g. control of current or voltage to keep battery in healthy state, cell balancing
• CPC Class Codes: H02J 7/0013 acting upon several batteries simultaneously or sequentially H02J7/1423 takes precedence
• CPC Class Codes: H02J 7/0069 Charging or discharging for charge maintenance, battery initiation or rejuvenation
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

The present invention concerns an apparatus comprising a charger circuit and a control circuit. The charger circuit may be configured to generate a first power down control signal and a second power down control signal in response to (i) a first charge signal, (ii) a second charge signal, (iii) a supply voltage, and (iv) a host control signal. The control circuit may be configured to generate the first charge signal and the second charge signal in response to a first battery signal and a second battery signal. The control circuit may enter a power down state in response to the host control signal initiating the power down state.

Claims

1. An apparatus comprising:

a charger circuit configured to generate a first power down control signal and a second power down control signal in response to (i) a first charge signal, (ii) a second charge signal, (iii) a supply voltage, and (iv) a host control signal; and

a control circuit configured to generate said first charge signal and said second charge signal in response to a first battery signal and a second battery signal, wherein (i) said apparatus enters a power down state in response to said host control signal initiating said power down state, (ii) said control circuit enters a sleep mode in said power down state and (iii) said control circuit disconnects operating power from said charger circuit in said power down state.

2. The apparatus according to claim 1, wherein said charger circuit receives power from (i) said supply voltage when said apparatus is in a first mode, and (ii) at least one of said first charge signal and said second charge signal when said apparatus is in a second mode.

3. The apparatus according to claim 2, wherein said control circuit enters said sleep mode when said apparatus is in said second mode and both said first charge signal and said second charge signal are removed from said charger circuit.

4. The apparatus according to claim 2, wherein said control circuit monitors a remaining battery charge of said first battery signal and said second battery signal according to a first checking protocol when said apparatus is in said first mode.

5. The apparatus according to claim 4, wherein said control circuit monitors said remaining battery charge of said first battery signal and said second battery signal according to a second checking protocol when said apparatus is in said power down state, wherein said second checking protocol uses less power than said first checking protocol.

6. The apparatus according to claim 2, wherein said control circuit comprises a first gauge circuit and a second gauge circuit configured to operate in a low power mode when said apparatus is in said power down state.

7. The apparatus according to claim 6, wherein said control circuit further comprises a first analog front end circuit and a second analog front end circuit configured to operate in said low power mode when said apparatus is in said power down state.

8. The apparatus according to claim 3, wherein (i) said first battery signal is received from a first battery pack and (ii) said second battery signal is received from a second battery pack.

9. The apparatus according to claim 1, wherein said host control signal is received through a control bus.

10. The apparatus according to claim 1, wherein said apparatus is configured to power a Redundant Array of Independent Disks (RAID) controller.

11. An apparatus comprising:

means for generating a first power down control signal and a second power down control signal in response to (i) a first charge signal, (ii) a second charge signal, (iii) a supply voltage, and (iv) a host control signal; and

means for generating said first charge signal and said second charge signal in response to a first battery signal and a second battery signal, wherein (i) said apparatus enters a power down state in response to said host control signal initiating said power down state, (ii) said means for generating said first charge signal and said second charge signal enters a sleep mode in said power down state and (iii) said means for generating said first charge signal and said second charge signal disconnects operating power from said means for generating said first power down control signal and said second power down control signal in said power down state.

12. An apparatus comprising:

an input circuit configured to generate a simulated power supply signal having an enabled state and a disabled state in response to a main power source and a host control signal received from a host bus; and

a charger circuit configured to avoid a power not good condition that disables operation of said charger circuit when said simulated power supply signal is in said enabled state, wherein (A) said charger circuit (i) is configured to charge a first battery and a second battery when said main power source is present, and (ii) protects an over voltage condition of said main power source from damaging said host bus and (B) said power not good condition occurs when initializing a power up sequence of said apparatus with said first battery unavailable, said second battery unavailable and said simulated power supply signal in said disabled state.

13. The apparatus according to claim 12, wherein said charger circuit is configured to operate using power received from said first battery and said second battery when said main power source is not present.

14. The apparatus according to claim 12, wherein said host bus comprises an I2C bus.

15. The apparatus according to claim 12, wherein said apparatus is configured to power a Redundant Array of Independent Disks (RAID) controller.

16. The apparatus according to claim 12, wherein said charger circuit is further configured to perform a coulomb counting when said simulated power supply signal is in said disabled state.

17. The apparatus according to claim 12, further comprising a control circuit configured to generate a sum signal conveying a highest available voltage from among said main power source, said first battery and said second battery.

18. The apparatus according to claim 17, wherein said input circuit is further configured to generate an output signal from said sum signal, said output signal powering a load connectable to said apparatus.

19. The apparatus according to claim 12, wherein said charger circuit is further configured to (i) control said charge and a discharge of said first battery by generating a plurality of first control signals on a first bus, (ii) control said charge and a discharge of said second battery by generating a plurality of second control signals on a second bus, (iii) draw an operating power from any available among said main power source, said first battery and said second battery and (iv) release both said first bus and said second bus when said operating power is unavailable.

20. The apparatus according to claim 19, further comprising a control circuit configured to (i) selectively switch a first battery signal of said first battery to and from said charger circuit in response to said first control signals, (ii) selectively switch a second battery signal of said second battery to and from said charger circuit in response to said second control signals and (iii) enter a sleep mode in response to said charger circuit releasing both said first bus and said second bus.