METAL-OXIDE-SEMICONDUCTOR CHIP AND FABRICATION METHOD THEREOF

• US 20110057254A1
• Filed: 09/10/2009
• Published: 03/10/2011
• Est. Priority Date: 09/10/2009
• Status: Active Grant

• Current Assignee: Niko Semiconductor Co., Ltd
• Original Assignee: Niko Semiconductor Co., Ltd
• Inventors: Tu, Kao-Way, Tsen, Kuo-Chang
• Granted Patent: US 8,169,019 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A metal-oxide-semiconductor chip having a semiconductor substrate, an epitaxial layer, at least a MOS cell, and a metal pattern layer is provided. The epitaxial layer is located on the semiconductor substrate and has an active region, a termination region, and a scribe line preserving region defined on an upper surface thereof. An etched sidewall of the epitaxial layer is located in the scribe line preserving region. The boundary portion of the upper surface of the semiconductor substrate is thus exposed. The MOS cell is located in the active region. The metal pattern layer is located on the epitaxial layer and has a gate pad coupled to the gate of the MOS cell, a source pad coupled to the source of the MOS cell, and a drain pattern, which is partly located on the upper surface of the semiconductor substrate.

Claims

1. A metal oxide semiconductor (MOS) chip, comprising:

a heavily doped semiconductor substrate, composing a drain doped region;

an epitaxial layer, which is located on the semiconductor substrate, having an active region, a termination region, and a scribe line preserving region defined on an upper surface thereof and having an etched sidewall in the scribed line preserving region extending to an upper surface of the semiconductor substrate, and a boundary portion of the upper surface of the semiconductor substrate being exposed;

at least a MOS cell, located in the active region; and

a metal pattern layer, located on the epitaxial layer and the exposed semiconductor substrate, the metal pattern layer having a gate pad, a source pad, and a drain pattern, wherein the gate pad is electrically connected to a gate electrode of the MOS cell, the source pad is electrically connected to a source electrode of the MOS cell, and at least a portion of the drain pattern is located on the upper surface of the semiconductor substrate.

2. The metal-oxide-semiconductor chip of claim 1, wherein the drain pattern is extended from the upper surface of the epitaxial layer to the upper surface of the semiconductor substrate.

3. The metal-oxide-semiconductor chip of claim 1, wherein the whole drain pattern is located on the upper surface of the semiconductor substrate.

4. The metal-oxide-semiconductor chip of claim 1, wherein the drain pattern is located outside the termination region.

5. The metal-oxide-semiconductor chip of claim 1, further comprising an insulating layer located on a lower surface of the semiconductor substrate.

6. The metal-oxide-semiconductor chip of claim 5, further comprising a thermal dissipation metallic structure located below the insulating layer.

7. The metal-oxide-semiconductor chip of claim 1, wherein a distance between a center of the epitaxial layer to an edge of the epitaxial layer is no greater than a thickness of the semiconductor substrate.

8. The metal-oxide-semiconductor chip of claim 1, wherein the epitaxial layer has a conduction type identical to that of the semiconductor substrate but has a lower dopant concentration.

9. A fabrication method of a metal-oxide-semiconductor chip, comprising the steps of:

providing a heavily doped semiconductor substrate;

forming an epitaxial layer on an upper surface of the semiconductor substrate, the epitaxial layer having a plurality of active regions, a plurality of termination regions and a scribe line preserving region defined on the upper surface thereof, wherein the active regions are surrounded by the termination regions respectively and the termination regions are surrounded by the scribe line preserving region;

forming a least one MOS cell in the active region;

forming a deep trench in the scribe line preserving region to expose a portion of the upper surface of the semiconductor substrate;

forming a metal pattern layer on the epitaxial layer and the exposed semiconductor substrate, the metal pattern layer having at least a gate pad, a source pad, and a drain pattern, wherein the gate pad and the source pad are located in the active region and electrically connected to a gate electrode and a source electrode of the MOS cell and at least a portion of the drain pattern is located on the upper surface of the semiconductor substrate; and

forming a scribe line along the scribe line preserving region to break the semiconductor substrate.

10. The fabrication method of the metal-oxide-semiconductor chip of claim 9, wherein the step of forming the metal pattern layer comprising:

forming a metal layer on the epitaxial layer and the semiconductor substrate; and

removing at least a portion of the metal layer on the epitaxial layer to form the gate pad and the source pad on the epitaxial layer.

11. The fabrication method of the metal-oxide-semiconductor chip of claim 10, wherein a portion of the metal layer on the semiconductor substrate is also removed in the step of removing the portion of the metal layer on the epitaxial layer.

12. The fabrication method of the metal-oxide-semiconductor chip of claim 9, wherein a width of the deep trench is greater than that of the scribe line.

13. The fabrication method of the metal-oxide-semiconductor chip of claim 9, wherein the active regions are arranged on the upper surface of the epitaxial layer in array.

14. The fabrication method of the metal-oxide-semiconductor chip of claim 9, wherein the drain pattern extends from the upper surface of the epitaxial layer to the upper surface of the semiconductor substrate.

15. The fabrication method of the metal-oxide-semiconductor chip of claim 9, wherein the whole drain pattern is located on the upper surface of the semiconductor substrate.

16. The fabrication method of metal-oxide-semiconductor chip of claim 9, wherein the drain pattern is located outside the termination region.

17. The fabrication method of the metal-oxide-semiconductor chip of claim 9 further comprising the step of forming an insulating layer on a lower surface of the semiconductor substrate.

18. The fabrication method of the metal-oxide-semiconductor chip of claim. 9, wherein a distance between the scribe line preserving region and a center of the active region is smaller than a thickness of the semiconductor substrate.