COMPOUND SEMICONDUCTOR SUBSTRATE

• US 20110062556A1
• Filed: 09/10/2010
• Published: 03/17/2011
• Est. Priority Date: 09/14/2009
• Status: Active Grant

• Current Assignee: CoorsTek KK (Trelleborg AB)
• Original Assignee: Covalent Materials Corporation
• Inventors: Suzuki, Shunichi, KOMIYAMA, Jun, Abe, Yoshihisa, Eriguchi, Kenichi, Oishi, Hiroshi, Yoshida, Akira
• Granted Patent: US 8,212,288 B2
• Time in Patent Office: Days
• US Class Current: 257/615
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/0254 Nitrides

Abstract

A compound semiconductor substrate which inhibits the generation of a crack or a warp and is preferable for a normally-off type high breakdown voltage device, arranged that a multilayer buffer layer 2 in which Al_xGa_1-xN single crystal layers (0.6≦X≦1.0) 21 containing carbon from 1×10¹⁸ atoms/cm³ to 1×10²¹ atoms/cm³ and Al_yGa_1-yN single crystal layers (0.1≦y≦0.5) 22 containing carbon from 1×10¹⁷ atoms/cm³ to 1×10²¹ atoms/cm³ are alternately and repeatedly stacked in order, and a nitride active layer 3 provided with an electron transport layer 31 having a carbon concentration of 5×10¹⁷ atoms/cm³ or less and an electron supply layer 32 are deposited on a Si single crystal substrate 1 in order. The carbon concentrations of the Al_xGa_1-xN single crystal layers 21 and that of the Al_yGa_1-yN single crystal layers 22 respectively decrease from the substrate 1 side towards the above-mentioned active layer 3 side. In this way, the compound semiconductor substrate is produced.

Claims

1. A compound semiconductor substrate, arranged such that a multilayer buffer layer in which Al_xGa_1-xN single crystal layers (0.6≦

X≦

1.0) containing carbon from 1×

10¹⁸ atoms/cm³ to 1×

10²¹ atoms/cm³ and Al_yGa_1-yN single crystal layers (0≦

y≦

0.5) containing carbon from 1×

10¹⁷ atoms/cm³ to 1×

10²¹ atoms/cm³ are alternately and repeatedly stacked in order, and a nitride active layer comprising an electron transport layer having a carbon concentration of 5×

10¹⁷ atoms/cm³ or less and an electron supply layer are deposited on a Si single crystal substrate in order, wherein

the carbon concentrations of said Al_xGa_1-xN single crystal layers and the carbon concentration of the Al_yGa_1-yN single crystal layers respectively decrease from said substrate side towards said active layer side.

2. The compound semiconductor substrate as claimed in claim 1, wherein said Al_yGa_1-yN single crystal layer is of 0.1≦

y≦

0.5.

3. The compound semiconductor substrate as claimed in claim 1, wherein the carbon concentration of said Al_xGa_1-xN single crystal layer is higher than the carbon concentration of Al_yGa_1-yN single crystal layer immediately above the former.

4. The compound semiconductor substrate as claimed in claim 2, wherein the carbon concentration of said Al_xGa_1-xN single crystal layer is higher than the carbon concentration of Al_yGa_1-yN single crystal layer immediately above the former.

5. The compound semiconductor substrate as claimed in claim 1, wherein said multilayer buffer layer contains boron from 5×

10¹⁶ atoms/cm³ to 1×

10¹⁹ atoms/cm³.

6. The compound semiconductor substrate as claimed in claim 2, wherein said multilayer buffer layer contains boron from 5×

10¹⁶ atoms/cm³ to 1×

10¹⁹ atoms/cm³.

7. The compound semiconductor substrate as claimed in claim 3, wherein said multilayer buffer layer contains boron from 5×

10¹⁶ atoms/cm³ to 1×

10¹⁹ atoms/cm³.

8. The compound semiconductor substrate as claimed in claim 4, wherein said multilayer buffer layer contains boron from 5×

10¹⁶ atoms/cm³ to 1×

10¹⁹ atoms/cm³.

9. The compound semiconductor substrate as claimed in claim 1, wherein said electron transport layer is an Al_zGa_1-zN single crystal layer (0≦

z≦

0.01).

10. The compound semiconductor substrate as claimed in claim 2, wherein said electron transport layer is an Al_zGa_1-zN single crystal layer (0≦

z≦

0.01).

11. The compound semiconductor substrate as claimed in claim 3, wherein said electron transport layer is an Al_zGa_1-zN single crystal layer (0≦

z≦

0.01).

12. The compound semiconductor substrate as claimed in claim 4, wherein said electron transport layer is an Al_zGa_1-zN single crystal layer (0≦

z≦

0.01).

13. The compound semiconductor substrate as claimed in claim 5, wherein said electron transport layer is an Al_zGa_1-zN single crystal layer (0≦

z≦

0.01).

14. The compound semiconductor substrate as claimed in claim 6, wherein said electron transport layer is an Al_zGa_1-zN single crystal layer (0≦

z≦

0.01).

15. The compound semiconductor substrate as claimed in claim 7, wherein said electron transport layer is an Al_zGa_1-zN single crystal layer (0≦

z≦

0.01).

16. The compound semiconductor substrate as claimed in claim 8, wherein said electron transport layer is an Al_zGa_1-zN single crystal layer (0≦

z≦

0.01).

17. The compound semiconductor substrate as claimed in claim 1, wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said substrate is used for a normally-off type switching device.

18. The compound semiconductor substrate as claimed in claim 2, wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said substrate is used for a normally-off type switching device.

19. The compound semiconductor substrate as claimed in claim 3, wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said substrate is used for a normally-off type switching device.

20. The compound semiconductor substrate as claimed in claim 4, wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said substrate is used for a normally-off type switching device.

21. The compound semiconductor substrate as claimed in claim 5, wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said substrate is used for a normally-off type switching device.

22. The compound semiconductor substrate as claimed in claim 6, wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said substrate is used for a normally-off type switching device.

23. The compound semiconductor substrate as claimed in claim 7, wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said substrate is used for a normally-off type switching device.

24. The compound semiconductor substrate as claimed in claim 8, wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said substrate is used for a normally-off type switching device.

25. The compound semiconductor substrate as claimed in claim 9, wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said substrate is used for a normally-off type switching device.

26. The compound semiconductor substrate as claimed in claim 10, wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said substrate is used for a normally-off type switching device.

27. The compound semiconductor substrate as claimed in claim 11, wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said substrate is used for a normally-off type switching device.

28. The compound semiconductor substrate as claimed in claim 12, wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said substrate is used for a normally-off type switching device.

29. The compound semiconductor substrate as claimed in claim 13, wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said substrate is used for a normally-off type switching device.

30. The compound semiconductor substrate as claimed in claim 14, wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said substrate is used for a normally-off type switching device.

31. The compound semiconductor substrate as claimed in claim 15, wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said substrate is used for a normally-off type switching device.

32. The compound semiconductor substrate as claimed in claim 16, wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said substrate is used for a normally-off type switching device.