CHIP PACKAGE AND PROCESS THEREOF

• US 20110068445A1
• Filed: 08/25/2010
• Published: 03/24/2011
• Est. Priority Date: 09/18/2009
• Status: Abandoned Application

• Current Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Original Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Inventors: Lin, Tai-Hung
• Application Number:
  US12/868,715
• Publication Number:
  US 20110068445A1
• Time in Patent Office: Days
• US Class Current: 257/675
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83101 as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 24/28 Structure, shape, material or disposition of the layer connectors prior to the connecting process
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 24/85 using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01083 : Bismuth [Bi]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A chip package and a process thereof are provided. The chip package includes a lead frame, a heat sink, a chip and a molding compound. The lead frame includes a chip pad and a plurality of leads, wherein the chip pad has a first surface and a second surface opposite thereto. The heat sink has a third surface and a fourth surface opposite thereto, wherein the lead frame is disposed on the third surface of the heat sink through the second surface of the chip pad, and the fourth surface of the heat sink is exposed. The chip is disposed on the first surface of the chip pad and electrically connected to each of the chip pad and the leads. The molding compound encapsulates the chip, the chip pad, the heat sink and a portion of each of the leads.

Claims

1. A chip package process, comprising:

providing a lead frame, the lead frame comprising a chip pad and a plurality of leads, wherein the chip pad has a first surface and a second surface which are opposite to each other;

disposing the lead frame on a third surface of a heat sink through the second surface of the chip pad, and electrically connecting the chip pad to the heat sink;

disposing a chip on the first surface of the chip pad, and electrically connecting the chip to each of the chip pad and the leads; and

forming a molding compound, so as to encapsulate the chip, the chip pad, the heat sink, and a portion of each of the leads, wherein the molding compound exposes a fourth surface of the heat sink, wherein the third surface and the fourth surface are opposite to each other.

2. The chip package process as claimed in claim 1, further comprising bonding the fourth surface of the heat sink to a bonding region of an electronic device, and electrically connecting the chip to the electronic device through the chip pad and the heat sink.

3. The chip package process as claimed in claim 2, wherein a method of bonding the heat sink and the electronic device comprises a surface mounting technology.

4. The chip package process as claimed in claim 2, wherein the bonding region of the electronic device has at least one through hole, so that the heat sink is exposed after the heat sink is bonded to the electronic device.

5. The chip package process as claimed in claim 2, wherein the electronic device comprises a circuit board, a testing pad, or a functional system.

6. The chip package process as claimed in claim 5, wherein the circuit board comprises a plurality of solder pads arranged in an array in the bonding region.

7. The chip package process as claimed in claim 2, wherein a shortest distance between the electronic device and the fourth surface of the heat sink is from 0.05 mm to 0.15 mm.

8. The chip package process as claimed in claim 2, wherein the electronic device contacts the fourth surface of the heat sink.

9. The chip package process as claimed in claim 1, further comprising forming an electrically conductive layer between the chip pad and the heat sink.

10. The chip package process as claimed in claim 9, wherein the electrically conductive layer is a bonding glue or an electrically conductive tape.

11. The chip package process as claimed in claim 1, wherein a method of electrically connecting the chip to the chip pad and the leads comprises wire bonding.

12. The chip package process as claimed in claim 1, wherein the heat sink has a central region and a peripheral region surrounding the central region, the central region is an electrically conductive region, the peripheral region is an insulation region, and the chip pad is disposed on the central region.

13. The chip package process as claimed in claim 12, wherein the central region is a lowered region and the peripheral region is a level region, the lowered region has a depth, there is a height difference between the chip pad and a top of the leads, and the depth is less then the height difference.

14. The chip package process as claimed in claim 13, wherein the depth of the lowered region is greater than 0 mm and less than 0.294 mm.

15. The chip package process as claimed in claim 12, further comprising performing an electroplating process on the central region, so as to form an electrically conductive layer on a surface of the central region.

16. The chip package process as claimed in claim 15, wherein a material of the electrically conductive layer comprises copper.

17. The chip package process as claimed in claim 15, further comprising forming an anti-oxidizing layer on the electrically conductive layer.

18. The chip package process as claimed in claim 17, wherein a method of forming the anti-oxidizing layer comprises electrolysis electroplating or chemical electroplating.

19. The chip package process as claimed in claim 17, wherein a material of the anti-oxidizing layer comprises nickel.

20. The chip package process as claimed in claim 12, further comprising performing an insulating process on the peripheral region.

21. The chip package process as claimed in claim 20, wherein the insulating process comprises attaching an insulation tape on the peripheral region.

22. The chip package process as claimed in claim 20, wherein the insulating process comprises selectively electroplating or performing an anodizing process on the peripheral region.

23. The chip package process as claimed in claim 1, further comprising the following steps prior to bonding the chip pad and the heat sink:

masking a central region of the third surface and the fourth surface by a masking layer, and exposing a remaining surface of the heat sink;

performing an insulating process on the heat sink which is partially masked, so as to form an insulation layer on the remaining surface of the heat sink; and

removing the masking layer.

24. The chip package process as claimed in claim 23, wherein the masking layer is a tape.

25. The chip package process as claimed in claim 23, wherein the insulating process comprises attaching an insulation tape on the remaining surface.

26. The chip package process as claimed in claim 23, wherein the insulating process comprises selectively electroplating or performing an anodizing process on the remaining surface.

27. The chip package process as claimed in claim 23, further comprising performing an electroplating process on the central region and the fourth surface after removing the masking layer, so as to form an electrically conductive layer on the central region and the fourth surface.

28. The chip package process as claimed in claim 27, wherein a material of the electrically conductive layer comprises copper.

29. The chip package process as claimed in claim 27, further comprising forming an anti-oxidizing layer on the electrically conductive layer.

30. The chip package process as claimed in claim 29, wherein a method of forming the anti-oxidizing layer comprises electrolysis electroplating or chemical electroplating.

31. The chip package process as claimed in claim 29, wherein a material of the anti-oxidizing layer comprises nickel.

32. A chip package, comprising:

a lead frame, comprising a chip pad and a plurality of leads, wherein the chip pad has a first surface and a second surface which are opposite to each other;

a heat sink, having a third surface and a fourth surface which are opposite to each other, wherein the lead frame is disposed on the third surface of the heat sink through the second surface of the chip pad, and the fourth surface of the heat sink is exposed;

a chip, disposed on the first surface of the chip pad and electrically connecting the chip to each of the chip pad and the leads; and

a molding compound, encapsulating the chip, the chip pad, the heat sink, and a portion of each of the leads.

33. The chip package as claimed in claim 32, further comprising an electronic device, wherein a bonding region of the electronic device is bonded to the fourth surface of the heat sink, so that the chip is electrically connected to the electronic device through the chip pad and the heat sink.

34. The chip package as claimed in claim 33, wherein the heat sink and the electronic device are bonded by a surface mounting technology.

35. The chip package as claimed in claim 33, wherein the bonding region of the electronic device has at least one through hole, so that the heat sink is exposed after the heat sink is bonded to the electronic device.

36. The chip package as claimed in claim 33, wherein the electronic device comprises a circuit board, a testing pad, or a functional system.

37. The chip package as claimed in claim 36, wherein the circuit board comprises a plurality of solder pads arranged in an array in the bonding region.

38. The chip package as claimed in claim 33, wherein a shortest distance between the electronic device and the fourth surface of the heat sink is from 0.05 mm to 0.15 mm.

39. The chip package as claimed in claim 33, wherein the electronic device contacts the fourth surface of the heat sink.

40. The chip package as claimed in claim 32, further comprising an electrically conductive layer between the chip pad and the heat sink.

41. The chip package as claimed in claim 40, wherein the electrically conductive layer is a bonding glue or an electrically conductive tape.

42. The chip package as claimed in claim 32, wherein the heat sink has a central region and a peripheral region surrounding the central region, the central region is an electrically conductive region, the peripheral region is an insulation region, and the chip pad is disposed on the central region.

43. The chip package as claimed in claim 42, wherein the central region is a lowered region and the peripheral region is a level region, the lowered region has a depth, there is a height difference between the chip pad and a top of the leads, and the depth is less then the height difference.

44. The chip package as claimed in claim 43, wherein the depth of the lowered region is greater than 0 mm and less than 0.294 mm.

45. The chip package as claimed in claim 42, wherein an electrically conductive layer is disposed on the central region and the fourth surface of the heat sink.

46. The chip package as claimed in claim 45, wherein the electrically conductive layer is formed by an electroplating process.

47. The chip package as claimed in claim 45, wherein a material of the electrically conductive layer comprises copper.

48. The chip package as claimed in claim 45, wherein an anti-oxidizing layer is further disposed on the electrically conductive layer.

49. The chip package as claimed in claim 48, wherein the anti-oxidizing layer is formed by electrolysis electroplating or chemical electroplating.

50. The chip package as claimed in claim 48, wherein a material of the anti-oxidizing layer comprises nickel.

51. The chip package as claimed in claim 42, wherein an insulation tape is attached on the peripheral region.

52. The chip package as claimed in claim 42, wherein selective electroplating or an anodizing process is performed on the peripheral region.

53. The chip package as claimed in claim 32, wherein selective electroplating or an anodizing process is performed on a remaining surface other than the third surface and the fourth surface of the heat sink.

54. The chip package as claimed in claim 32, wherein an insulating tape is attached on a remaining surface other than the third surface and the fourth surface of the heat sink.

55. The chip package as claimed in claim 32, wherein the heat sink comprises a first portion and a second portion, a center of the first portion is a hollowed portion, the second portion is embedded in the hollowed portion of the first portion, and the chip pad is bonded to the second portion.

56. The chip package as claimed in claim 55, wherein a material of the first portion comprises aluminum.

57. The chip package as claimed in claim 55, wherein a material of the second portion comprises a material which is electrically conductive and able to be plated with tin.

58. The chip package as claimed in claim 55, wherein a material of the second portion comprises copper.

59. The chip package as claimed in claim 55, wherein an anti-oxidizing layer is disposed on a surface of the second portion.

60. The chip package as claimed in claim 59, wherein a method of forming the anti-oxidizing layer comprises electrolysis electroplating or chemical electroplating.

61. The chip package as claimed in claim 59, wherein a material of the anti-oxidizing layer comprises nickel.

62. The chip package as claimed in claim 55, wherein an insulating process is performed on a surface of the first portion.

63. The chip package as claimed in claim 62, wherein the insulating process comprises attaching an insulation tape on a surface of the first portion.

64. The chip package as claimed in claim 62, wherein the insulating process comprises selectively electroplating or performing an anodizing process on the surface of the first portion.