FAIL SAFE ADAPTIVE VOLTAGE/FREQUENCY SYSTEM

• US 20110068858A1
• Filed: 09/18/2009
• Published: 03/24/2011
• Est. Priority Date: 09/18/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Inventors: Chatterjee, Kallol, Kumar, Promod, Parthasarathy, Chittoor, Chawla, Nitin
• Granted Patent: US 8,154,335 B2
• Time in Patent Office: Days
• US Class Current: 327/538
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.

Claims

1. A system, comprising:

a system on chip (SoC) having a digital domain;

an adaptive voltage scaling circuit including a critical path replica circuit with respect to the digital domain, the critical path replica circuit generating a margin signal, the adaptive voltage scaling circuit varying a bias voltage applied to the digital domain of the system on chip in response to the margin signal; and

a fail-safe timing sensor for a critical path circuit within the digital domain of the system on chip, the timing sensor generating a flag signal;

wherein the adaptive voltage scaling circuit varies the bias voltage applied to the digital domain of the system on chip in response to the flag signal.

2. The system of claim 1 wherein the varying of the bias voltage by the adaptive voltage scaling circuit comprises decreasing bias voltage to recover available margin in the digital domain in response to the margin signal and increasing bias voltage for a recovery operation in response to the flag signal.

3. The system of claim 2 wherein the fail-safe timing sensor is adapted to detect violation of a safe timing margin on the SoC digital domain resulting from the decrease in applied bias voltage from the adaptive voltage scaling circuit.

4. The system of claim 3 wherein the fail-safe timing sensor is a critical path end point monitor circuit.

5. The system of claim 4 wherein the critical path end point monitor circuit comprises:

a clock input;

a data input;

a first delay coupled to the clock input to generate a delay clock signal;

a second delay coupled to the data input to generate a delay data signal;

a window generator coupled to receive the clock input and delay clock signal so as to generate a timing window; and

a transition detector coupled to receive the delay data signal and timing window and determine whether to generate the flag signal in response to the delay data signal changing state within the timing window.

6. The system of claim 1 wherein the digital domain includes a critical path circuit with a high speed option, the high speed option for the critical path circuit being enabled in response to the flag signal.

7. The system of claim 6 wherein the high speed option comprises circuitry selected from the group consisting of additional drive capacity and reduced threshold voltage circuitry.

8. The system of claim 6 further including a switch circuit operable responsive to the flag signal to switch between the critical path circuit and circuitry with the high speed option.

9. A system, comprising:

a system on chip (SoC) having a digital domain;

an adaptive frequency scaling circuit including a critical path replica circuit with respect to the digital domain, the critical path replica circuit generating a margin signal, the adaptive frequency scaling circuit varying a clock frequency applied to the digital domain of the system on chip in response to the margin signal; and

a fail-safe timing sensor for a critical path circuit within the digital domain of the system on chip, the timing sensor generating a flag signal;

wherein the adaptive frequency scaling circuit varies the clock frequency applied to the digital domain of the system on chip in response to the flag signal.

10. The system of claim 9 wherein the varying of the clock frequency by the adaptive frequency scaling circuit comprises increasing clock frequency to recover available margin in the digital domain in response to the margin signal and decreasing clock frequency for a recovery operation in response to the flag signal.

11. The system of claim 10 wherein the fail-safe timing sensor is adapted to detect violation of a safe timing margin on the SoC digital domain resulting from the increase in applied clock frequency from the adaptive voltage scaling circuit.

12. The system of claim 11 wherein the fail-safe timing sensor is a critical path end point monitor circuit.

13. The system of claim 12 wherein the critical path end point monitor circuit comprises:

a clock input;

a data input;

a first delay coupled to the clock input to generate a delay clock signal;

a second delay coupled to the data input to generate a delay data signal;

a window generator coupled to receive the clock input and delay clock signal so as to generate a timing window; and

a transition detector coupled to receive the delay data signal and timing window and determine whether to generate the flag signal in response to the delay data signal changing state within the timing window.

14. The system of claim 9 wherein the digital domain includes a critical path circuit with a high speed option, the high speed option for the critical path circuit being enabled in response to the flag signal.

15. The system of claim 14 wherein the high speed option comprises circuitry selected from the group consisting of additional drive capacity and reduced threshold voltage circuitry.

16. The system of claim 14 further including a switch circuit operable responsive to the flag signal to switch between the critical path circuit and circuitry with the high speed option.

17. A process, comprising:

performing adaptive voltage scaling to vary a bias voltage applied to a digital domain of a system on chip (SoC) in response to margin information provided by a critical path replica circuit;

sensing timing margin within the digital domain of the system on chip;

generating a flag signal responsive to a sensed violation of a safe timing margin on the SoC digital domain resulting from the variation in applied bias voltage;

varying the bias voltage applied to the digital domain of the system on chip in response to the flag signal.

18. The process of claim 17 wherein the adaptive voltage scaling to vary the bias voltage comprises decreasing the bias voltage to recover available margin in the digital domain and wherein varying the bias voltage in response to the flag signal comprises increasing the bias voltage for a recovery operation.

19. The process of claim 17 further comprising activating a high speed option of a critical path circuit within the digital domain in response to the flag signal.

20. A process, comprising:

performing adaptive frequency scaling to vary a clock frequency applied to a digital domain of a system on chip (SoC) in response to margin information provided by a critical path replica circuit;

sensing timing margin within the digital domain of the system on chip;

generating a flag signal responsive to a sensed violation of a safe timing margin on the SoC digital domain resulting from the variation in applied clock frequency;

varying the clock frequency applied to the digital domain of the system on chip in response to the flag signal.

21. The process of claim 20 wherein the adaptive frequency scaling to vary the clock frequency comprises increasing the clock frequency to recover available margin in the digital domain and wherein varying the clock frequency in response to the flag signal comprises decreasing the clock frequency for a recovery operation.

22. The process of claim 20 further comprising activating a high speed option of a critical path circuit within the digital domain in response to the flag signal.

23. A process for guided fail-safe voltage or frequency scaling, comprising:

monitoring a network of timing sensors in a digital domain, each timing sensor being set with individual timing margins whose violation results in the generation of a flag signal;

applying a voltage or frequency scaling direction and adjustment step size in response to a generated flag signal, wherein the voltage or frequency scaling direction and adjustment step size are set for a recovery operation uniquely associated with each of the timing sensors in the digital domain.

24. The process of claim 23, wherein the individual timing margins of each timing sensor are defined by certain timing windows and signal edge transition conditions.

25. The process of claim 23, wherein applying voltage or frequency scaling direction and adjustment step size comprises locally applying scaling within a portion of the digital domain associated with the timing sensor which generated the flag signal.

26. The process of claim 23, wherein monitoring the network of timing sensors comprises monitoring a plurality of sensors simultaneously.

27. The process of claim 23, wherein monitoring the network of timing sensors comprises monitoring a plurality of sensors in a temporally sequential manner.

28. The process of claim 27, wherein monitoring and applying comprise:

first determining if a timing margin of a first timing sensor having an individual timing margin set by a first timing window has been violated;

if not, applying a first voltage or frequency scaling direction and adjustment step size for a first delay period before repeating the step of first determining;

if so, second determining if a timing margin of a second timing sensor having an individual timing margin set by a second timing window has been violated; and

if not, applying a second voltage or frequency scaling direction and adjustment step size for a second delay period before repeating the step of second determining.

29. A process, comprising:

selecting a sufficient set of end points within a digital domain of a system on chip to be monitored by fail safe in-situ sensors;

exploiting the end points under different circuit or application scenarios so as to excite the critical path terminating in these end points;

sensing timing margin within the digital domain of the system on chip using the un situ sensors;

generating a flag signal responsive to a sensed violation of a safe timing margin on the system on chip digital domain.

30. The process of claim 29 wherein exploiting comprises applying testing values of voltage and/or frequency to the digital domain, the process further comprising monitoring the generated flag signal in response to the applied testing values to ensure the flag signal is correctly set.

31. The process of claim 29 wherein exploiting comprises applying testing values of voltage and/or frequency to the digital domain during a known operation phase of the digital domain, said known operational phase comprising one of a reset initialization or a power sequencing or an idle operation.