High voltage MOSFET diode reverse recovery by minimizing P-body charges

• US 20110073906A1
• Filed: 09/30/2009
• Published: 03/31/2011
• Est. Priority Date: 09/30/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Guan, Lingpeng, Bobde, Madhur, Bhalla, Anup
• Granted Patent: US 8,324,053 B2
• Time in Patent Office: Days
• US Class Current: 257/147
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions; and f) etching contact trenches into the source, body contact, and body regions.

Claims

1. A semiconductor power device disposed in a semiconductor substrate comprises an active cell area and a termination area comprising:

a semiconductor substrate comprising a bottom substrate layer, and a top substrate layer situated on top of said bottom substrate layer;

a planar gate comprising a patterned polysilicon layer disposed on a top surface of said semiconductor substrate;

a patterned field oxide layer disposed in said termination area and also in said active cell area at a gap area away from said patterned polysilicon layer on said top surface of said semiconductor substrate;

body regions disposed in said semiconductor substrate substantially diffused from a region aligned with said gap area below said top surface and extended to regions below said patterned polysilicon layer and said patterned field oxide layer, said body region having an opposite conductivity type as said top substrate layer;

source regions encompassed in and having an opposite conductivity type from said body regions;

body contact regions encompassed in and having a higher dopant concentration than said body region surrounding said source regions, the body contact regions being located below said doped source regions, wherein said field oxide layer in the active cell area is removed after forming the body, source and body contact regions;

a contact trench formed next to said planar gate, wherein said contact trench is etched into the semiconductor substrate and allows contact to be made laterally to the source and body contact regions, said contact trenches being formed partially in an area previously occupied by said field oxide layer in said active cell area; and

a bottom electrode formed at the bottom of the semiconductor substrate.

2. The semiconductor power device of claim 1 further comprising:

a patterned Schottky metal layer covering said contact trench for contacting said body contact regions and said source regions, and also the top substrate layer to form integrated Schottky diodes for said semiconductor power device in said active cell area.

3. The semiconductor power device of claim 2 further comprising:

shallow body-dopant implantations adjacent to said body regions immediately under said contact trenches to adjust the Schottky barrier height.

4. The semiconductor power device of claim 1 wherein:

said semiconductor power device further comprises a metal oxide semiconductor field effect transistor (MOSFET) power device wherein said bottom electrode is a drain electrode.

5. The semiconductor power device of claim 1 wherein:

said semiconductor power device further comprises an insulated gate bipolar transistor (IGBT) power device.

6. The semiconductor power device of claim 1 wherein:

said semiconductor power device further comprises an insulated gate bipolar transistor (IGBT) power device wherein said bottom substrate layer has the same conductivity type as the body region and wherein said bottom substrate layer further comprises a source-type dopant region connecting said top substrate layer to said bottom electrode.

7. The semiconductor power device of claim 6 wherein:

said semiconductor power device further comprises a Schottky diode formed between two gates.

8. The semiconductor power device of claim 1 wherein:

said semiconductor power device further comprises a superjunction semiconductor power device comprising charge balanced alternating N-type and P-type dopant columns in said top substrate layer.

9. The semiconductor device of claim 1 further comprising:

a body-type dopant region adjacent to the body region and immediately below the contact trench to reduce the curvature of the body region.

10. A method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area comprising:

growing and patterning a field oxide layer in said termination area and also in said active cell area on a top surface of said semiconductor substrate using a first mask;

forming a gate oxide layer on said top surface of said semiconductor substrate;

depositing and patterning with a second mask a polysilicon layer on said gate oxide at a gap distance away from said field oxide layer, wherein said polysilicon layer acts as planar gates in the active area;

performing a blank body dopant implant to form body dopant regions in said semiconductor substrate substantially aligned with said gap area followed by diffusing said body dopant regions into body regions in said semiconductor substrate;

forming body contact regions encompassed in and having a higher dopant concentration than said body regions, wherein said field oxide region reduces the amount of P-body charges found in the semiconductor power device due to forming the body and body contact regions;

applying a source mask as the third mask to implant source regions having a conductivity opposite to said body regions with said source regions encompassed in said body regions and located above said high concentration body contact regions;

depositing an insulation layer on top of said semiconductor power device and applying a contact mask as the fourth mask to open contact openings and remove said field oxide, and etching into the semiconductor substrate to form contact trenches, wherein said contact trenches further reduce the amount of P-body charges in the device; and

depositing a metal layer filling in said contact trenches to contact said body regions and said source regions, and patterning said metal layer with a fifth mask.

11. The method of claim 10 wherein:

said step of depositing a metal layer filling in said contact trenches further comprises depositing a Schottky metal layer to form integrated Schottky diodes.

12. The method of claim 11 further comprising:

forming shallow body-type regions adjacent to said body regions immediately below said contact trenches to adjust the Schottky barrier height.

13. The method of claim 10 wherein:

said step of performing a blank body dopant implant to form body regions further comprises performing a blank body dopant implant at a lower concentration than usual, and compensating by forming said body contact regions with a higher concentration than normal in order to reduce the amount of body-dopant charges available for high level injection while maintaining control of the gate threshold voltage.

14. The method of claim 10 wherein:

said step of manufacturing said semiconductor power device further comprises a step of manufacturing a MOSFET power device.

15. The method of claim 10 wherein:

said step of manufacturing said semiconductor power device further comprises a step of manufacturing an IGBT power device.

16. The method of claim 15 wherein:

said applying a contact mask as the fourth mask to open contact openings further comprises forming an opening between polysilicon gates to form a Schottky diode trench.

17. The method of claim 10 wherein:

said step of manufacturing said semiconductor power device further comprises a step of manufacturing a superjunction power device.

18. The method of claim 17 further comprising prior to said step of growing and patterning a field oxide layer:

forming charge balanced alternating p-type and n-type columns in said semiconductor substrate.

19. The method of claim 10 further comprising a step of:

forming a body-type dopant region adjacent to the body region and below said contact trench to reduce the curvature of the body region.

20. The method of claim 10 wherein:

said step of depositing and patterning with a second mask a polysilicon layer further comprises depositing and patterning with a second mask a polysilicon layer in the termination area, wherein the polysilicon layer formed in the termination area act as field plates.

21. The method of claim 10 further comprising a step of:

forming a metal layer on the bottom of the semiconductor device to form a bottom electrode.