Method for the Connection of Two Wafers, and a Wafer Arrangement

• US 20110079911A1
• Filed: 12/13/2010
• Published: 04/07/2011
• Est. Priority Date: 02/27/2004
• Status: Active Grant

• Current Assignee: OSRAM OLED GMBH (Ams-Osram AG)
• Original Assignee: Osram Opto Semiconductors GmbH (Ams-Osram AG)
• Inventors: STREUBEL, Klaus
• Granted Patent: US 8,471,385 B2
• Time in Patent Office: Days
• US Class Current: 257/772
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 2224/81224 using a laser
• CPC Class Codes: H01L 2224/83224 using a laser
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate

Abstract

A method for the connection of two wafers in which a contact area is formed between the two wafers by placing the two wafers one on top of the other. The contact area is heated locally and for a limited time. A wafer arrangement comprises two wafers which have been placed one on top of the other and between whose opposite surfaces a contact area is located. The wafers are connected to one another at selected areas of the contact area.

Claims

1. A wafer arrangement, comprising:

two wafers placed one on top of the other; and

a contact area between the two wafers;

wherein

the two wafers are connected to one another at selected connection areas of the contact area,

at least one of the two wafers is a silicon wafer, a germanium wafer, a gallium arsenide wafer, an InP wafer, a ceramic wafer or a GaP wafer,

a mechanical joint between the two wafers is mediated or effected by a material between the two wafers, wherein said material is applied at least in said selected connection areas,

at least one of the two wafers comprises two or more individual layers, and

at least one of the two or more individual layers is an epitaxially applied layer comprising an active layer configured to produce or to detect radiation, and wherein at least one of the two or more individual layers is part of an optoelectronic component.

2. The wafer arrangement as claimed in claim 1, wherein the two wafers are connected to one another at junction points at the contact area.

3. The wafer arrangement as claimed in claim 2, wherein the junction points are arranged at nodes of a regular network.

4. The wafer arrangement as claimed in claim 1, wherein the material is applied on the entire surface of at least one of the wafers.

5. The wafer arrangement as claimed in claim 1, wherein one of the wafers is a growth substrate for the epitaxially applied layer.

6. The wafer arrangement as claimed in claim 1, wherein each of the two wafers has the same length in a lateral direction.

7. The wafer arrangement as claimed in claim 1, wherein at least one additional material is applied to each of the wafers, and the at least one additional material applied to a first wafer of said two wafers is different from the at least one additional material applied to a second wafer of said two wafers.

8. The wafer arrangement as claimed in claim 7, wherein the at least one additional material is solder.

9. The method as claimed in claim 8, wherein the solder is selected from the following materials:

Au, AuSn, Pd, In and Pt.

10. The wafer arrangement as claimed in claim 7, wherein the at least one additional material is mixed in a melt.

11. The wafer arrangement as claimed in claim 1, wherein at least one of the two wafers is transparent with respect to a laser beam.

12. The wafer arrangement as claimed in claim 11, wherein the material is not transparent to the laser beam.

13. The wafer arrangement as claimed in claim 1, wherein the epitaxially applied layer comprises at least one of the following semiconductor materials:

GaInN, AlGaAs, AlGaInP, GaP, InP, InGaAs, InGaAsP, GaN and AlGaInN.

14. The wafer arrangement as claimed in claim 1, wherein at least one of the two wafers comprises at least one of the following materials:

Mo, Cu and CuW.

15. The wafer arrangement as claimed in claim 1, wherein a sum of the surface areas of the contact area in which the two wafers are connected to one another is less than a sum of the surface areas of the contact area in which there is no connection between the two wafers.

16. The wafer arrangement as claimed in claim 1, wherein the two wafers are not connected to one another at separation points of the wafer arrangement.

17. A wafer arrangement, comprising:

two wafers placed one on top of the other; and

a contact area between the two wafers, wherein the two wafers are connected to one another at selected connection areas of the contact area.

18. The wafer arrangement as claimed in claim 17, wherein the two wafers are connected to one another at junction points at the contact area.

19. The wafer arrangement as claimed in claim 18, wherein the junction points are arranged at nodes of a regular network.

20. The wafer arrangement as claimed in claim 17, wherein at least one of the wafers includes at least one temperature-sensitive layer.

21. The wafer arrangement as claimed in claim 17, wherein a sum of the surface areas of the contact area in which the two wafers are connected to one another is less than a sum of the surface areas of the contact area in which there is no connection between the two wafers.

22. The wafer arrangement as claimed in claim 17, wherein the two wafers are not connected to one another at separation points of the wafer arrangement.