Method and Apparatus for Implantable Lead

• US 20110082530A1
• Filed: 04/02/2010
• Published: 04/07/2011
• Est. Priority Date: 04/02/2009
• Status: Abandoned Application

• Current Assignee: Proteus Digital Health, Inc. (Otsuka Holdings Company Limited)
• Original Assignee: Proteus Digital Health, Inc. (Otsuka Holdings Company Limited)
• Inventors: Zdeblick, Mark
• Application Number:
  US12/997,556
• Publication Number:
  US 20110082530A1
• Time in Patent Office: Days
• US Class Current: 607/116
• CPC Class Codes: A61N 1/0551 Spinal or peripheral nerve electrodes
• CPC Class Codes: A61N 1/36071 Pain

Abstract

In one embodiment of the invention, an implantable lead is provided. It has a plurality of satellites along its length, each satellite having at least one electrode and having as many as four electrodes at each satellite. Each satellite has a chip which controls the manner in which electrodes are or are not connected with a conductor within the lead. In an embodiment a control signal is transmitted through the connector of the first and along the at least one conductor to the chips of the satellites, thereby configuring at each chip a respective impedance between the at least one conductor and the respective at least one electrode. Sub-sequently, a pacing current is passed through the connector of the first lead and along the at least one conductor, and at each chip passing a portion of the pacing current through the respective impedance to the respective at least one electrode.

Claims

1. A method for use with a first implantable lead, the first lead having a length and having at least first, second, and third satellites along its length, each satellite having at least one electrode, each satellite having a chip, the first lead having at least one conductor communicatively coupled with the chip of each satellite and extending to an end of the first lead, the at least one conductor connected to a respective connector at the end of the first lead, the method comprising the steps of:

transmitting a control signal through the connector of the first lead and along the at least one conductor to the chips of the at least first, second, and third satellites, thereby configuring at each chip a respective impedance between the at least one conductor and the respective at least one electrode;

passing a pacing current through the connector of the first lead and along the at least one conductor, and at each chip passing a portion of the pacing current through the respective impedance to the respective at least one electrode.

2. The method of claim 1 wherein the current passed through the electrode of the first one of the satellites differs from the current passed through the electrode of the second one of the satellites.

3. The method of claim 1 wherein the current passed through the electrode of the first one of the satellites is approximately the same as the current passed through the electrode of the second one of the satellites.

4. The method of claim 1 wherein prior to the transmitting step, the at least one electrode is disabled, and wherein at the end of the control signal, the at least one electrode is enabled.

5. The method of claim 1 wherein the control signal comprises a message corresponding to each chip, each message comprising an address portion addressing one or another of the chips, and wherein the message further comprises a configuration portion configuring the addressed chip with its respective impedance.

6. The method of claim 5 wherein the configuration portion comprises a value comprising at least three bits indicative of a desired impedance, and wherein the chip further comprises means mapping the at-least-three-bit value to an impedance value, the mapped impedance values selected to give rise to respective currents through tissue that are approximately linearly related to the at-least-three-bit value.

7. The method of claim 1 wherein the configuring step further comprises electrically connecting the electrode of the first one of the satellites to the at least one conductor.

8. The method of claim 1 wherein the configuring step further comprises disposing the electrode of the first one of the satellites at a high impedance relative to the at least one conductor.

9. The method of claim 1 wherein the first one of the satellites has at least first and second electrodes, and wherein the configuring step further comprises electrically connecting the first electrode of the first one of the satellites to the second electrode of the first one of the satellites.

10. The method of claim 1 wherein the number of conductors is two, thereby defining first and second conductors.

11. The method of claim 10 wherein the configuring step further comprises electrically connecting the electrode of the first one of the satellites to the first conductor.

12. The method of claim 10 wherein the configuring step further comprises electrically connecting the electrode of the first one of the satellites to the second conductor.

13. The method of claim 10 wherein the configuring step further comprises disposing the electrode of the first one of the satellites at a high impedance relative to the first conductor and at a high impedance relative to the second conductor.

14. The method of claim 10 wherein the first one of the satellites has at least first and second electrodes, and wherein the configuring step further comprises electrically connecting the first electrode of the first one of the satellites to the first conductor and electrically connecting the second electrode of the first one of the satellites to the second conductor.

15. The method of claim 1 for use with a second implantable lead, the second lead having a length and having at least first, second, and third satellites along its length, each satellite having at least one electrode, each satellite having a chip, the second lead having at least one conductor communicatively coupled with the chip of each satellite and extending to an end of the second lead, the at least one conductor connected to a respective connector at the end of the second lead, the method comprising the steps of:

transmitting a control signal through the connector of the second lead and along the at least one conductor to the chips of the at least first, second, and third satellites, thereby configuring at each chip a respective impedance between the at least one conductor and the respective at least one electrode, the respective impedance of a first one of the satellites differing from the respective impedance of the second one of the satellites;

passing a pacing current through the connector of the second lead and along the at least one conductor, and at each chip passing a portion of the pacing current through the respective impedance to the respective at least one electrode.

16. The method of claim 15 wherein the transmitting of the pacing current through the connector of the first lead happens when the pacing current through the connector of the second lead happens.

17. The method of claim 15 wherein the transmitting of the control signal through the connector of the second lead happens after the transmitting of the control signal through the connector of the first lead.

18. The method of claim 15 for use with a third implantable lead, the third lead having a length and having at least first, second, and third satellites along its length, each satellite having at least one electrode, each satellite having a chip, the third lead having at least one conductor communicatively coupled with the chip of each satellite and extending to an end of the third lead, the at least one conductor connected to a respective connector at the end of the third lead, the method comprising the steps of:

transmitting a control signal through the connector of the third lead and along the at least one conductor to the chips of the at least first, second, and third satellites, thereby configuring at each chip a respective impedance between the at least one conductor and the respective at least one electrode, the respective impedance of a first one of the satellites differing from the respective impedance of the second one of the satellites;

passing a pacing current through the connector of the third lead and along the at least one conductor, and at each chip passing a portion of the pacing current through the respective impedance to the respective at least one electrode.

19. The method of claim 18 wherein the transmitting of the pacing current through the connector of the first lead happens when the pacing current through the connector of the second lead happens, and the transmitting of the pacing current through the connector of the second lead happens when the pacing current through the connector of the third lead happens,

20. The method of claim 18 wherein the transmitting of the control signal through the connector of the third lead happens after the transmitting of the control signal through the connector of the first lead, and happens after the transmitting of the control signal through the connector of the second lead.

21. The method of claim 1 further comprising the steps, performed before the transmitting and passing steps, of:

removing the lead from a sterile wrapping;

implanting the lead in tissue; and

connecting the connector of the lead to an implantable device.

22. The method of claim 21 wherein the connecting step comes after the implanting step.

23. A method for use with a first implantable lead, the first lead having a length and having at least first, second, and third satellites along its length, each satellite having at least one electrode, each satellite having a chip, the first lead having at least one conductor communicatively coupled with the chip of each satellite and extending to an end of the first lead, the at least one conductor connected to a respective connector at the end of the first lead, the method comprising the steps of:

transmitting a control signal through the connector of the first lead and along the at least one conductor to the chips of the at least first, second, and third satellites, thereby configuring at each chip a respective impedance between the at least one conductor and the respective at least one electrode, the respective impedance of a first one of the satellites differing from the respective impedance of the second one of the satellites;

passing a pacing current through the connector of the first lead and along the at least one conductor, and at each chip passing a portion of the pacing current through the respective impedance to the respective at least one electrode.

24. Apparatus comprising an implantable first lead, the first lead having a length and having at least first, second, and third satellites along its length,

each satellite having at least one electrode,

each satellite having a chip,

the first lead having at least one conductor communicatively coupled with the chip of each satellite and extending to an end of the first lead,

the at least one conductor connected to a respective connector at the end of the first lead,

each chip responsive to a control signal transmitted through the connector of the first lead and along the at least one conductor, by configuring at the chip a respective impedance between the at least one conductor and the respective at least one electrode;

each chip responsive to a pacing current passed through the connector of the first lead and along the at least one conductor, by passing a portion of the pacing current through the respective impedance to the respective at least one electrode.

25. The apparatus of claim 24 wherein the respective impedance is high impedance.

26. The apparatus of claim 24 wherein the satellite has at least first and second electrodes, and wherein the configuring further comprises electrically connecting the first electrode of the first one of the satellites to the second electrode of the satellite.

27. The apparatus of claim 24 wherein the control signal comprises messages, each message comprising an address portion addressing one or another of the chips, and wherein the message further comprises a configuration portion configuring the addressed chip with its respective impedance.

28. The apparatus of claim 27 wherein the configuration portion comprises a value comprising at least three bits indicative of a desired impedance, and wherein the chip further comprises means mapping the at-least-three-bit value to an impedance value, the mapped impedance values selected to give rise to respective currents through tissue that are approximately linearly related to the at-least-three-bit value.

29. The apparatus of claim 24 wherein the number of conductors is two.

30. The apparatus of claim 29 wherein the configuring further comprises electrically connecting the electrode of the first one of the satellites to the first conductor.

31. The apparatus of claim 29 wherein the configuring further comprises electrically connecting the electrode of the first one of the satellites to the second conductor.

32. The apparatus of claim 29 wherein the configuring further comprises disposing the electrode of the first one of the satellites at a high impedance relative to the first conductor and at a high impedance relative to the second conductor.

33. The apparatus of claim 29 wherein the first one of the satellites has at least first and second electrodes, and wherein the configuring step further comprises electrically connecting the first electrode of the first one of the satellites to the first conductor and electrically connecting the second electrode of the first one of the satellites to the second conductor.

34. The apparatus of claim 24 wherein the lead is sterile, and is contained within removable packaging preserving the sterility.