RELIABLE COMMUNICATIONS IN ON-CHIP NETWORKS

• US 20110087943A1
• Filed: 10/12/2009
• Published: 04/14/2011
• Est. Priority Date: 10/12/2009
• Status: Active Grant

• Current Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC), Intellectual Ventures Asia Pte Ltd (Intellectual Ventures LLC)
• Original Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Inventors: Mutlu, Onur, Mangione-Smith, William H.
• Granted Patent: US 8,473,818 B2
• Time in Patent Office: Days
• US Class Current: 714/748
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 15/17325 Synchronisation; Hardware support therefor intertask synchronisation G06F9/52
• CPC Class Codes: H04L 1/18 Automatic repetition systems, e.g. Van Duuren systems

Abstract

Techniques for reliable communication in an on-chip network of a multi-core processor are provided. Packets are tagged with tags that define reliability requirements for the packets. The packets are routed in accordance with the reliability requirements. The reliability requirements and routing using them can ensure reliable communication in the on-chip network.

Claims

1. In a chip having an on-chip network providing communication among a plurality of cores, a method for delivering a packet in the on-chip network, the method comprising:

originating the packet at an originating core included in the plurality of cores in the on-chip network, the core including a processor and a switch;

tagging the packet with a tag that defines a reliability requirement for the packet, wherein the reliability requirement controls delivery of the packet in the on-chip network; and

delivering the packet to a destination core in compliance with the reliability requirement, wherein the reliability requirement enables the on-chip network to dynamically adjust performance of the on-chip network in the delivery of the packet.

2. The method of claim 1, wherein the reliability requirement includes a bit indicating whether reliable transport is required for the packet in the on-chip network.

3. The method of claim 2, wherein the bit is set by at least one of an application, an operating system, the switch, a processor, or a virtual machine monitor.

4. The method of claim 1, wherein the reliability requirement is applied to at least one of the packets, all packets from a stream of packets in an application, all packets associated with the application, or all packets from the originating core.

5. The method of claim 1, further comprising resending the packet when the packet fails to be delivered to the destination core.

7. The method of claim 1, further comprising responding to a packet failure with an application through an interface with the core.

8. The method of claim 7, further comprising cancelling delivery of the packet according to an age of the packet.

9. The method of claim 8, further comprising replacing the packet with an updated packet.

11. The method of claim 1, further comprising storing a record of packet delivery failures, wherein the record is used to determine reliability requirements for subsequent packets.

6. The method of claim 6, further comprising resending the packet by at least one of a network switch, a core, or a plurality of network switches and cores in cooperation.

10. The method of claim 6, wherein a packet failure is asynchronous such that threads can work on other tasks in the on-chip network and also respond to the packet failure.

12. A method for routing a packet in an on-chip network, the method comprising:

receiving a packet at a core of a multi-core processor from an originating core, the core including at least a processor and a switch for routing packets;

examining a reliability requirement associated with the packet, wherein the reliability requirement identifies delivery options for the packet in the on-chip network; and

transmitting the packet in the on-chip network to a destination core while complying with the reliability requirement associated with the packet.

13. The method of claim 12, wherein examining a reliability requirement associated with the packet further comprises complying with the reliability requirement.

14. The method of claim 13, wherein the reliability requirement requires storing the packet in a buffer of the core until receipt of the packet is confirmed.

15. The method of claim 13, wherein the reliability requirement requires requesting that the packet be resent in the event of packet failure.

16. The method of claim 12, wherein the reliability requirement requires confirmation of receipt of the packet before transmitting subsequent packets.

17. The method of claim 12, further comprising cancelling the packet according to an age of the packet in the event of packet failure.

18. The method of claim 12, further comprising replacing the packet with an updated packet in the event of packet failure.

19. The method of claim 12, further comprising:

storing data associated with packet failures in the on-chip network; and

adjusting the reliability requirement of subsequent packets based on the data.

20. The method of claim 19, wherein adjusting reliability requirement comprises mapping delivery tasks to specific cores in the on-chip network.

21. A processing device having an on-chip network for routing a packet, the processor comprising:

a plurality of connections;

a plurality of cores connected by the plurality of connections to form the on-chip network, each core including an originating core and a destination core, each core including a processor and a network switch, wherein the originating core generates the packet and tags the packet with a tag that defines a reliability requirement, wherein the packet is delivered to the destination core according to the reliability requirement.

22. The processing device of claim 21, wherein at least one of the originating core, the destination core, or a core in a delivery path of the packet changes settings of the network switch, wherein the settings are defined in the reliability requirement.

23. The processing device of claim 22, wherein the settings include at least one of a clock speed for the network switch or a voltage level for the network switch.

24. The processing device of claim 21, wherein each core in a delivery path of the packet in the on-chip network from the originating core to the destination core evaluates the reliability requirement for compliance.

25. The processing device of claim 24, further comprising storing the packet in a cache of at least one core in the delivery path.