PWM Limiter Circuit

• US 20110095787A1
• Filed: 10/27/2010
• Published: 04/28/2011
• Est. Priority Date: 10/28/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohmaru, Takuro, Ito, Yoshiaki
• Granted Patent: US 8,587,270 B2
• Time in Patent Office: Days
• US Class Current: 327/35
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

The duty ratio of a PWM signal is prevented from being zero immediately after the start of PWM control, for example. A PWM limiter circuit has a structure with which a signal output from the PWM limiter circuit can be prevented from being higher than a certain value or lower than a certain value. The PWM limiter circuit includes a comparator circuit, a controller circuit, and a switch circuit. The highest duty ratio reference voltage V_refH is input to a first input terminal. The lowest duty ratio reference voltage V_refL is input to a second input terminal. Voltage V_err output from an error amplifier is input to a third input terminal.

Claims

1. A PWM limiter circuit comprising:

a first terminal to which highest duty ratio reference voltage is input;

a second terminal to which lowest duty ratio reference voltage is input;

a comparator for comparing a voltage input to a third terminal with the highest duty ratio reference voltage or the lowest duty ratio reference voltage;

a first switch which is turned on when the voltage input to the third terminal is higher than the highest duty ratio reference voltage;

a second switch which is turned on when the voltage input to the third terminal is lower than the lowest duty ratio reference voltage;

a third switch which is turned on when the voltage input to the third terminal is higher than the lowest duty ratio reference voltage and lower than the highest duty ratio reference voltage; and

an output terminal electrically connected to the first switch, the second switch, and the third switch,

wherein the first switch is electrically connected to the first terminal, the second switch is electrically connected to the second terminal, and the third switch is electrically connected to the third terminal.

2. The PWM limiter circuit according to claim 1,

wherein the first switch is formed using a p-channel transistor, and

wherein the second switch is formed using an n-channel transistor.

3. A DC-DC converter comprising:

a PWM control circuit comprising;

a PWM limiter circuit comprising;

a first terminal to which highest duty ratio reference voltage is input;

a second terminal to which lowest duty ratio reference voltage is input;

a comparator for comparing a voltage input to a third terminal with the highest duty ratio reference voltage or the lowest duty ratio reference voltage;

a first switch which is turned on when the voltage input to the third terminal is higher than the highest duty ratio reference voltage;

a second switch which is turned on when the voltage input to the third terminal is lower than the lowest duty ratio reference voltage;

a third switch which is turned on when the voltage input to the third terminal is higher than the lowest duty ratio reference voltage and lower than the highest duty ratio reference voltage; and

an output terminal electrically connected to the first switch, the second switch, and the third switch,

wherein the first switch is electrically connected to the first terminal, the second switch is electrically connected to the second terminal, and the third switch is electrically connected to the third terminal.

4. The PWM limiter circuit according to claim 3,

wherein the first switch is formed using a p-channel transistor, and

wherein the second switch is formed using an n-channel transistor.