Non-Volatile Memory And Method With Accelerated Post-Write Read To Manage Errors

• US 20110096601A1
• Filed: 09/01/2010
• Published: 04/28/2011
• Est. Priority Date: 10/28/2009
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Chen, Jian, Gavens, Lee M.
• Granted Patent: US 8,634,240 B2
• Time in Patent Office: Days
• US Class Current: 365/185.09
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. An error management provides reading and checking the copy after copying to the second portion. If the copy has excessive error bits, it is repeated in a different location either in the second or first portion. The reading and checking of the copy is accelerated by reading only a sample of it. The sample is selected from a subset of the copy having its own ECC and estimated to represent a worst error rate among the copy it is sampling. One embodiment has the sample taken from one bit of each multi-bit memory cell of a group.

Claims

1. A method of operating a non-volatile memory, comprising:

providing multiple groups of memory cells, the memory cells in each group for operating in parallel;

programming multiple subsets of data into a first group of memory cells, each subset of data being provided with an ECC;

selecting a sample of the data programmed in the first group of memory cells, the sample being selected from a subset of data said multiple subsets of data programmed into the first group;

reading said sample;

checking said sample for errors, and

reprogramming said multiple subsets of data into a second group of memory cells whenever the errors checked from the sample is more than a predetermined number of error bits.

2. The method as in claim 1, wherein:

the first group of memory cells resides on a word line.

3. The method as in claim 1, wherein:

the first group forms a block of memory cells that is a minimum erase unit.

4. The method as in claim 1, wherein:

the sample is a subset of data estimated to have a highest error rate among said multiple subsets of data programmed into the first group.

5. The method as in claim 1, wherein:

each memory cells of the first group stores n bits of data;

said programming multiple subsets of data stores n data pages into the first group of memory cells, each data page constituted by one bit from each memory cell in the first group.

6. The method as in claim 1, wherein:

n is equal to 3.

7. The method as in claim 1, wherein:

said checking for errors include checking the ECC of the sample to determine the number of error bits.

8. The method as in claim 1, further comprising:

configuring said non-volatile memory into first and second portions, the first portion having memory cells operating with less error rate but lower density storage compared to the second portion; and

wherein;

said first and second groups of memory cells are in the first portion; and

said second group of memory cells is in the second portion.

9. The method as in claim 1, further comprising:

configuring said non-volatile memory into first and second portions, the first portion having memory cells operating with less error rate but lower density storage compared to the second portion; and

wherein;

said first group of memory cells is in the first portion; and

said second group of memory cells is in the second portion.

10. The method as in claim 1, wherein:

the memory is further organized into multiple rows of NAND chains;

each NAND chain being a column of a string of daisy-chained memory cells terminating at a source terminal and a drain terminal; and

the sample is a subset of data stored at memory cells closest to the source terminal of each NAND chain.

11. The method as in claim 1, wherein:

the memory is further organized into multiple rows of NAND chains;

each NAND chain being a column of a string of daisy-chained memory cells terminating at a source terminal and a drain terminal; and

the sample is a subset of data stored at memory cells closest to the drain terminal of each NAND chain.

12. A non-volatile memory, comprising:

multiple groups of memory cells, the memory cells in each group for operating in parallel;

a programming circuit for programming multiple subsets of data into a first group of memory cells, each subset of data being provided with an ECC;

a sample of the data programmed in the first group of memory cells, the sample being selected from a subset of data said multiple subsets of data programmed into the first group;

a reading circuit for reading said sample;

an ECC decoder for checking errors in said sample, and

a reprogramming circuit for reprogramming said multiple subsets of data into a second group of memory cells whenever the errors checked from the sample is more than a predetermined number of error bits.

13. The non-volatile memory as in claim 12, wherein:

the first group of memory cells resides on a word line.

14. The non-volatile memory as in claim 12, wherein:

the first group forms a block of memory cells that is a minimum erase unit.

15. The non-volatile memory as in claim 12, wherein:

the sample is a subset of data estimated to have a highest error rate among said multiple subsets of data programmed into the first group.

16. The non-volatile memory as in claim 12, wherein:

each memory cells of the first group stores n bits of data;

said programming multiple subsets of data stores n data pages into the first group of memory cells, each data page constituted by one bit from each memory cell in the first group.

17. The non-volatile memory as in claim 12 wherein:

n is equal to 3.

18. The non-volatile memory as in claim 12, wherein:

said ECC decoder checks the ECC of the sample to determine the number of error bits.

19. The non-volatile memory as in claim 12, further comprising:

first and second portions, the first portion having memory cells operating with less error rate but lower density storage compared to the second portion; and

wherein;

said first and second groups of memory cells are in the first portion; and

said second group of memory cells is in the second portion.

20. The non-volatile memory as in claim 12, further comprising:

first and second portions, the first portion having memory cells operating with less error rate but lower density storage compared to the second portion; and

wherein;

said first group of memory cells is in the first portion; and

said second group of memory cells is in the second portion.

21. The non-volatile memory as in claim 12, wherein:

the memory is further organized into multiple rows of NAND chains;

each NAND chain being a column of a string of daisy-chained memory cells terminating at a source terminal and a drain terminal; and

the sample is a subset of data stored at memory cells closest to the source terminal of each NAND chain.

22. The non-volatile memory as in claim 12, wherein:

the memory is further organized into multiple rows of NAND chains;

each NAND chain being a column of a string of daisy-chained memory cells terminating at a source terminal and a drain terminal; and

the sample is a subset of data stored at memory cells closest to the drain terminal of each NAND chain.