SYSTEM AND METHOD FOR DYNAMICALLY SWITCHING BETWEEN LOW AND HIGH FREQUENCY REFERENCE CLOCK TO PLL AND MINIMIZING PLL OUTPUT FREQUENCY CHANGES

• US 20110102030A1
• Filed: 11/02/2009
• Published: 05/05/2011
• Est. Priority Date: 11/02/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Goldman, Stanley, Ramaswamy, Srinath
• Granted Patent: US 8,125,253 B2
• Time in Patent Office: Days
• US Class Current: 327/156
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/193 the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider

Abstract

A circuit is provided for use with a clock signal having a plurality of clock pulses, each clock pulse having a rising edge and a falling edge. The circuit is operable to receive a reference signal and to output an output signal. The circuit includes an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter portion and a voltage controlled oscillator portion. The input divider portion is arranged to receive the reference signal and is operable to output a divided reference signal. The feedback divider portion is arranged to receive the output signal and is operable to output a divided feedback signal. The phase detector portion is operable to output a phase detector signal based on the divided reference signal and the divided feedback signal. The loop compensation filter portion is operable to output a tuning signal based on the phase detector signal. The voltage controlled oscillator portion is operable to output the output signal based on the tuning signal. The phase detector portion is further operable to change the phase detector signal based on the input divider portion receiving the control signal and the feedback divider portion receiving the control signal, and further based on the control signal and a rising edge of a clock pulse.

Claims

1. A circuit for use with a control signal and a clock signal having a plurality of clock pulses, each clock pulse having a rising edge and a falling edge, said circuit being operable to receive a reference signal and to output an output signal, said circuit comprising:

an input divider portion arranged to receive the control signal and the reference signal and operable to output a divided reference signal;

a feedback divider portion arranged to receive the control signal and the output signal and operable to output a divided feedback signal;

a phase detector portion operable to receive the control signal and to output a phase detector signal based on the divided reference signal and the divided feedback signal;

a loop compensation filter portion operable to output a fining signal based on the phase detector signal; and

a voltage controlled oscillator portion operable to output the output signal based on the tuning signal,

wherein said phase detector portion is further operable to change the phase detector signal based on said input divider portion receiving the control signal and said feedback divider portion receiving the control signal, and further based on the control signal and a rising edge of a clock pulse.

2. The circuit of claim 1, wherein said loop compensation filter portion comprises a first filter portion, a second filter portion and an operational amplifier portion.

3. The circuit of claim 2,

wherein said operational amplifier portion comprises a first input and a second input,

wherein said first filter portion is operable to pass a first portion of the phase detector signal to the first input,

wherein said second filter portion is operable to pass a second portion of the phase detector signal to the second input, and

wherein said operational amplifier portion is operable to output the tuning signal based on a difference between the first portion of the phase detector signal and the second portion of the phase detector signal.

4. The circuit of claim 3,

wherein said first filter portion comprises a first capacitor operable to store a first charge, and

wherein said second filter portion comprises a second capacitor operable to store a second charge.

5. The circuit of claim 4, further comprising:

a first switch operable to be in one of a first open position and a first closed position; and

a second switch operable to be in one of a second open position and a second closed position,

wherein when said first switch is in the first open position, said first capacitor is operable to maintain the first charge,

wherein when said second switch is in the second open position, said second capacitor is operable to maintain the second charge,

wherein when said first switch is in the first closed position, a first direct current path to ground is provided to said first capacitor, and

wherein when said second switch is in the second closed position, a second direct current path to ground is provided to said second capacitor.

6. The circuit of claim 1,

wherein said input divider portion comprises a first programmable counter operable to divide the reference signal by an integer M, where M>

0, and

wherein said feedback divider portion comprises a second programmable counter operable to divide the output signal by an integer N, where N>

0.

7. The circuit of claim 1,

wherein said input divider portion is further arranged to receive a CLRZ signal based on a rising edge of a pulse within the clock signal and is further operable to be enabled to output the divided reference signal based on the CLRZ signal, and

wherein said feedback divider portion is further arranged to receive the CLRZ signal based on the rising edge of the pulse within the clock signal and is further operable to be enabled to output the divided feedback signal based on the CLRZ signal.

8. A circuit for use with a clock signal having a plurality of clock pulses, each clock pulse having a rising edge and a falling edge, said circuit being operable to receive a reference signal and to output an output signal, said circuit comprising:

an input divider portion arranged to receive the reference signal and operable to output a divided reference signal;

a feedback divider portion arranged to receive the output signal and operable to output a divided feedback signal;

a phase detector portion operable to output a phase detector signal based on the divided reference signal and the divided feedback signal; and

a voltage controlled oscillator portion operable to output the output signal based on the phase detector signal,

wherein said input divider portion is further arranged to receive a CLRZ signal based on a rising edge of a pulse within the clock signal and is further operable to be enabled to output the divided reference signal based on the CLRZ signal, and

wherein said feedback divider portion is further arranged to receive the CLRZ signal based on the rising edge of the pulse within the clock signal and is further operable to be enabled to output the divided feedback signal based on the CLRZ signal.

9. The circuit of claim 8, further comprising a loop compensation filter portion having a first filter portion, a second filter portion and an operational amplifier portion.

10. The circuit of claim 9,

wherein said operational amplifier portion comprises a first input and a second input,

wherein said first filter portion is operable to pass a first portion of the phase detector signal to the first input,

wherein said second filter portion is operable to pass a second portion of the phase detector signal to the second input, and

wherein said operational amplifier portion is operable to output the tuning signal based on a difference between the first portion of the phase detector signal and the second portion of the phase detector signal.

11. The circuit of claim 10,

wherein said first filter portion comprises a first capacitor operable to store a first charge, and

wherein said second filter portion comprises a second capacitor operable to store a second charge.

12. The circuit of claim 11, further comprising:

a first switch operable to be in one of a first open position and a first closed position; and

a second switch operable to be in one of a second open position and a second closed position,

wherein when said first switch is in the first open position, said first capacitor is operable to maintain the first charge,

wherein when said second switch is in the second open position, said second, capacitor is operable to maintain the second charge,

wherein when said first switch is in the first closed position, a first direct current path to ground is provided to said first capacitor, and

wherein when said second switch is in the second closed position, a second direct current path to ground is provided to said second capacitor.

13. The circuit of claim 8,

wherein said input divider portion comprises a first programmable counter operable to divide the reference signal by an integer M, where M>

0, and

wherein said feedback divider portion comprises a second programmable counter operable to divide the output signal by an integer N, where N>

0.

14. A circuit for use with a clock signal having a plurality of clock pulses, each clock pulse having a rising edge and a falling edge, said circuit being operable to receive a first reference signal, to receive a second reference signal and to output an output signal, the first reference signal having a first frequency, the second reference signal having a second frequency, the first frequency being less than the second frequency, said circuit comprising:

a synchronization portion arranged to receive the first reference signal and the second reference signal and operable to output a CLRZ signal and to output a selected reference signal;

a feedback divider portion arranged to receive the output signal and operable to output a divided feedback signal;

a phase detector portion operable to output a phase detector signal based on the selected reference signal and the divided feedback signal; and

a voltage controlled oscillator portion operable to output the output signal based on the phase detector signal,

wherein said feedback divider portion is further arranged to receive the CLRZ signal based on the rising edge of the pulse within the clock signal and is further operable to be enabled to output the divided feedback signal based on the CLRZ signal.

15. The circuit of claim 14, wherein said loop compensation filter portion comprises a first filter portion, a second filter portion and an operational amplifier portion.

16. The circuit of claim 15,

wherein said operational amplifier portion comprises a first input and a second input,

wherein said first filter portion is operable to pass a first portion of the phase detector signal to the first input,

wherein said second filter portion is operable to pass a second portion of the phase detector signal to the second input, and

wherein said operational amplifier portion is operable to output the tuning signal based on a difference between the first portion of the phase detector signal and the second portion of the phase detector signal.

17. The circuit of claim 16,

wherein said first filter portion comprises a first capacitor operable to store a first charge, and

wherein said second filter portion comprises a second capacitor operable to store a second charge.

18. The circuit of claim 17, further comprising:

a first switch operable to be in one of a first open position and a first closed position; and

a second switch operable to be in one of a second open position and a second closed position,

wherein when said first switch is in the first open position, said first capacitor is operable to maintain the first charge,

wherein when said second switch is in the second open position, said second capacitor is operable to maintain the second charge,

wherein when said first switch is in the first closed position, a first direct current path to ground is provided to said first capacitor, and

wherein when said second switch is in the second closed position, a second direct current path to ground is provided to said second capacitor.

19. The circuit of claim 14, wherein said feedback divider portion comprises a second programmable counter operable to divide the output signal by an integer N, where N>

0.

20. The circuit of claim 14, wherein said synchronization portion includes a multiplexer arranged to receive the first reference signal and the second reference signal.