Stacked pre-driver amplifier

• US 20110109393A1
• Filed: 11/12/2009
• Published: 05/12/2011
• Est. Priority Date: 11/12/2009
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Nobbe, Dan William, Adamski, Jaroslaw Edward, Sharma, Vikas
• Granted Patent: US 8,106,711 B2
• Time in Patent Office: Days
• US Class Current: 330/295
• CPC Class Codes: H03F 1/0216 Continuous control
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 2200/408 the output amplifying stage of an amplifier comprising three power stages
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/21106 An input signal being distributed in parallel over the inputs of a plurality of power amplifiers
• CPC Class Codes: H03F 2203/21142 Output signals of a plurality of power amplifiers are parallel combined to a common output
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/3028 with symmetrical driving of the end stage
• CPC Class Codes: H03F 3/423 with MOSFET's

Abstract

A stacked pre-driver stage and a power amplifier including the stacked pre-driver stage are described. The stacked pre-driver stage comprises stacked pre-drivers arranged in series between a supply voltage and a reference voltage. Each pre-driver includes a pre-driving amplifier, together with MOS transistors. Each pre-driver is subject, in operation, to a voltage difference which is inferior to a maximum allowed use voltage of the MOS transistors with a largely reduced voltage drop across the regulator included in the power amplifier.

Claims

1. An amplifier for amplifying an input signal, comprising:

a first amplifying stage connected with a second amplifying stage, wherein;

the first amplifying stage comprises at least two amplifying circuits connected in series, each amplifying circuit receiving as input the input signal, each amplifying circuit having an output, and

the outputs of the amplifying circuits of the first amplifying stage are input to the second amplifying stage.

2. The amplifier of claim 1, wherein the first amplifying stage is a pre-driver stage of the power amplifier and the second amplifying stage is a final driver stage of the power amplifier.

3. The amplifier of claim 1, wherein the amplifier is adapted to be powered, during an operative condition, by a power supply generating a supply voltage and a supply current.

4. The amplifier of claim 3, further comprising a regulator located between the power supply and the first amplifying stage.

5. The amplifier of claim 4, wherein voltage drop across the regulator is negligible when compared to voltage drop across the first amplifying stage.

6. The amplifier of claim 3, wherein each amplifying circuit receives as further input the supply current.

7. The amplifier of claim 1, wherein the outputs of the amplifying circuits of the first amplifying stage are capacitively combined.

8. The amplifier of claim 1, wherein the second amplifying stage comprises at least one power amplifier.

9. The amplifier of claim 8, wherein the second amplifying stage comprises one power amplifier, the output of the power amplifier being the output of the amplifier.

10. The amplifier of claim 8, wherein the second amplifying stage comprises at least two power amplifiers.

11. The amplifier of claim 10, wherein each power amplifier of the at least two power amplifiers is in correspondence with a respective amplifying circuit of the at least two amplifying circuits.

12. The amplifier of claim 10, wherein each power amplifier has an output, and wherein the outputs of the power amplifiers are combined to form an output of the amplifier.

13. The amplifier of claim 11, wherein each power amplifier has an output, and wherein the outputs of the power amplifiers are combined to form an output of the amplifier.

14. The amplifier of claim 12, wherein the outputs of the power amplifiers are combined in a power combiner.

15. The amplifier of claim 13, wherein the outputs of the power amplifiers are combined in a power combiner.

16. The amplifier of claim 1, wherein the at least two amplifying circuits are two amplifying circuits.

17. The amplifier of claim 16, wherein the second amplifier stage comprises two power amplifiers.

18. The amplifier of claim 17, wherein each power amplifier of the two power amplifiers is in correspondence with a respective amplifying circuit of the two amplifying circuits.

19. The amplifier of claim 16, wherein the output of a first amplifying circuit of the two amplifying circuits is opposite in phase with the output of the second amplifying circuit of the two amplifying circuits.

20. The amplifier of claim 19, wherein the first amplifying circuit comprises a non-inverting amplifier and the second amplifying circuit comprises an inverting amplifier.

21. he amplifier of claim 20, wherein each power amplifier has an output, and wherein the outputs of the power amplifiers are combined to form an output of the amplifier.

22. The amplifier of claim 18, wherein the output of a first amplifying circuit of the two amplifying circuits is opposite in phase with the output of the second amplifying circuit of the two amplifying circuits.

23. The amplifier of claim 22, wherein the first amplifying circuit comprises a non-inverting amplifier and the second amplifying circuit comprises an inverting amplifier.

24. The amplifier of claim 10, wherein the at least two power amplifiers are connected in series.

25. The amplifier of claim 24, wherein the amplifier is adapted to be powered, during an operative condition, by a power supply generating a supply voltage and a supply current.

26. The amplifier of claim 25, wherein each power amplifier is powered the same supply current.

27. The amplifier of claim 26, wherein each power amplifier is powered by the same supply voltage.

28. The amplifier of claim 19, wherein the second amplifying stage comprises a differential power amplifier.

29. The amplifier of claim 4, wherein the regulator is adapted to switch the first amplifying stage between an ON condition and an OFF condition.

30. A power amplifier for amplifying an input carrier signal, comprising:

a stacked pre-driver stage, the stacked pre-driver stage comprising a plurality of stacked pre-drivers arranged in series between a supply voltage and a reference voltage, each pre-driver comprising a pre-driving amplifier, the input carrier signal being fed, in operation, to each pre-driver, outputs of the stacked pre-drivers being combined to form an output of the stacked pre-driver stage;

a driver stage receiving the output of the stacked pre-driver stage; and

a regulator located between a power supply supplying the supply voltage and the stacked pre-driver stage,

wherein each pre-driver comprises MOS transistors and is subject to a voltage difference which is inferior to a maximum allowed use voltage of the MOS transistors,

and wherein voltage drop across the regulator is small when compared to the voltage difference to which the stacked pre-driver stage is subjected.

31. The power amplifier of claim 30, wherein the output of the driver stage is the output of the power amplifier.

32. The power amplifier of claim 30, wherein the outputs of the stacked pre-drivers are capacitively combined.

33. The power amplifier of claim 30, wherein the plurality of stacked pre-drivers arranged in series are a first pre-driver and a second pre-driver, the first pre-driver arranged between a first voltage between the supply voltage and a reference voltage and a second voltage between the supply voltage and the reference voltage, the first voltage being higher than the second voltage, the second pre-driver arranged between the second voltage and the reference voltage.

34. The power amplifier of claim 33, wherein the second voltage is a substantially constant voltage.

35. The power amplifier of claim 30, wherein the input carrier signal is fed to each pre-driver through a capacitive coupling.

36. The power amplifier of claim 30, wherein, in each pre-driver, the MOS transistors comprise a p-channel MOS transistor and an n-channel MOS transistor connected to each other and with the pre-driver amplifier.

37. The power amplifier of claim 36, wherein, for each pre-driver, the output of the pre-driver amplifier is connected with the gate of the p-channel MOS and the gate of the n-channel MOS, and the drains of the p-channel MOS and the n-channel MOS are connected to each other and form the output of the pre-driver.

38. The power amplifier of claim 30, wherein the plurality of stacked pre-drivers are n stacked pre-drivers, and wherein the supply voltage is configurable to be up to n×

Vuse, Vuse being said maximum voltage difference to which said MOS transistors are subject, n being≧

2.

39. A power amplifier for amplifying an input carrier signal, comprising:

a stacked pre-driver stage, the stacked pre-driver stage comprising a plurality of stacked pre-drivers arranged in series between a supply voltage and a reference voltage, each pre-driver comprising a pre-driving amplifier, the input carrier signal being fed, in operation, to each pre-driver, outputs of the stacked pre-drivers forming outputs of the stacked pre-driver stage;

a driver stage receiving the outputs of the stacked pre-driver stage, the driver stage comprising a plurality of power amplifiers, each power amplifier being in correspondence of a pre-driver and receiving a respective output from a respective pre-driver, outputs of the power amplifiers forming outputs of the driver stage;

a regulator located between a power supply supplying the supply voltage and the stacked pre-driver stage, and

a power combiner that combines the outputs of the driver stage,

wherein each pre-driver comprises MOS transistors and is subject to a voltage difference which is inferior to a maximum allowed use voltage of the MOS transistors,

and wherein voltage drop across the regulator is small when compared to the voltage difference to which the stacked pre-driver stage is subjected.

40. The power amplifier of claim 39, wherein the output of the power combiner is the output of the power amplifier.

41. The power amplifier of claim 39, wherein the plurality of stacked pre-drivers arranged in series are a first pre-driver and a second pre-driver, the first pre-driver arranged between a first voltage between the supply voltage and a reference voltage and a second voltage between the supply voltage and the reference voltage, the first voltage being higher than the second voltage, the second pre-driver arranged between the second voltage and the reference voltage.

42. The power amplifier of claim 41, wherein the second voltage is a substantially constant voltage.

43. The power amplifier of claim 39, wherein the input carrier signal is fed to each pre-driver through a capacitive coupling.

44. The power amplifier of claim 39, wherein, in each pre-driver, the MOS transistors comprise a p-channel MOS transistor and an n-channel MOS transistor connected to each other and with the pre-driver amplifier.

45. The power amplifier of claim 44, wherein, for each pre-driver, the output of the pre-driver amplifier is connected with the gate of the p-channel MOS and the gate of the n-channel MOS, and the drains of the p-channel MOS and the n-channel MOS are connected to each other and form the output of the pre-driver.

46. The power amplifier of claim 39, wherein the plurality of stacked pre-drivers are n stacked pre-drivers, and wherein the supply voltage is configurable to be up to n×

Vuse, Vuse being said maximum voltage difference to which said MOS transistors are subject, n being≧

2.

47. A power amplifier for amplifying an input carrier signal, comprising:

a stacked pre-driver stage, the stacked pre-driver stage comprising two stacked pre-drivers arranged in series between a supply voltage and a reference voltage, the input carrier signal being fed, in operation, to each pre-driver, each pre-driver comprising a pre-driving amplifier, outputs of the stacked pre-drivers forming outputs of the stacked pre-driver stage, the output of a first pre-driver being opposite in phase to the output of the second pre-driver;

a driver stage receiving the outputs of the stacked pre-driver stage, the driver stage comprising two power amplifiers, a first power amplifier being in correspondence of the first pre-driver and receiving the output of the first pre-driver, the second power amplifier being in correspondence of the second pre-driver and receiving the output of the second pre-driver;

a regulator located between a power supply supplying the supply voltage and the stacked pre-driver stage, and

a power combiner that combines the outputs of the first power amplifier and second power amplifier,

wherein each pre-driver comprises MOS transistors and is subject to a voltage difference which is inferior to a maximum allowed use voltage of the MOS transistors,

and wherein voltage drop across the regulator is small when compared to the voltage difference to which the stacked pre-driver stage is subjected.

48. The power amplifier of claim 47, wherein the first pre-driver is arranged between a first voltage between the supply voltage and a reference voltage and a second voltage between the supply voltage and the reference voltage, the first voltage being higher than the second voltage, and the second pre-driver is arranged between the second voltage and the reference voltage.

49. The power amplifier of claim 48, wherein the second voltage is a substantially constant voltage.

50. The power amplifier of claim 48, wherein the input carrier signal is fed to each pre-driver.

51. The power amplifier of claim 47, wherein, in each pre-driver, the MOS transistors comprise a p-channel MOS transistor and an n-channel MOS transistor connected to each other and with the pre-driver amplifier.

52. The power amplifier of claim 51, wherein, for each pre-driver, the output of the pre-driver amplifier is connected with the gate of the p-channel MOS and the gate of the n-channel MOS, and the drains of the p-channel MOS and the n-channel MOS are connected to each other and form the output of the pre-driver.

53. A power amplifier for amplifying an input carrier signal, comprising:

a stacked pre-driver stage, the stacked pre-driver stage comprising two stacked pre-drivers arranged in series between a supply voltage and a reference voltage, each pre-driver comprising a pre-driving amplifier, the input carrier signal being fed, in operation, to each pre-driver, outputs of the stacked pre-drivers forming outputs of the stacked pre-driver stage;

a driver stage receiving the outputs of the stacked pre-driver stage, the driver stage comprising two power amplifiers, a first power amplifier being in correspondence of the first pre-driver and receiving the output of the first pre-driver, the second power amplifier being in correspondence of the second pre-driver and receiving the output of the second pre-driver, each of the first and second power amplifier being powered with the supply voltage and the reference voltage;

a regulator located between a power supply supplying the supply voltage and the stacked pre-driver stage, and

a power combiner that combines the outputs of the driver stage,

wherein each pre-driver comprises MOS transistors and is subject to a voltage difference which is inferior to a maximum allowed use voltage of the MOS transistors,

and wherein voltage drop across the regulator is small when compared to the voltage difference to which the stacked pre-driver stage is subjected.

54. The power amplifier of claim 53, wherein the output of a first pre-driver is opposite in phase to the output of the second pre-driver.

55. The power amplifier of claim 53, wherein the first pre-driver is arranged between a first voltage between the supply voltage and a reference voltage and a second voltage between the supply voltage and the reference voltage, the first voltage being higher than the second voltage, and the second pre-driver is arranged between the second voltage and the reference voltage.

56. The power amplifier of claim 55, wherein the second voltage is a substantially constant voltage.

57. The power amplifier of claim 53, wherein the input carrier signal is fed to each pre-driver through a capacitive coupling.

58. The power amplifier of claim 53, wherein the first power amplifier receives the output of the first pre-driver through a capacitive coupling, and the second power amplifier receives the output of the second pre-driver through a capacitive coupling.

59. The power amplifier of claim 53, wherein, in each pre-driver, the MOS transistors comprise a p-channel MOS transistor and an n-channel MOS transistor connected to each other and with the pre-driver amplifier.

60. The power amplifier of claim 59, wherein, for each pre-driver, the output of the pre-driver amplifier is connected with the gate of the p-channel MOS and the gate of the n-channel MOS, and the drains of the p-channel MOS and the n-channel MOS are connected to each other and form the output of the pre-driver.

61. A stacked pre-driver stage adapted to be used in a power amplifier circuit for amplification of an input signal, the power amplifier comprising a regulator connected with the stacked pre-driver stage, the stacked pre-driver stage comprising:

a plurality of stacked pre-drivers to be arranged in series between a supply voltage and a reference voltage, each pre-driver comprising a pre-driving amplifier, the input signal being fed, in operation, to each pre-driver,

wherein each pre-driver comprises MOS transistors and is subject, in operation, to a voltage difference which is inferior to a maximum allowed use voltage of the MOS transistors,

and wherein voltage drop across the regulator is small when compared to the voltage difference to which the plurality of stacked pre-drivers is subjected.