ACTIVE PIXEL SENSOR WITH MIXED ANALOG AND DIGITAL SIGNAL INTEGRATION

• US 20110115960A1
• Filed: 12/10/2010
• Published: 05/19/2011
• Est. Priority Date: 10/29/1998
• Status: Active Grant

• Current Assignee: Vladimir Berezin
• Original Assignee: Vladimir Berezin
• Inventors: Berezin, Vladimir
• Granted Patent: US 8,462,248 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/587 acquired sequentially, e.g. using the combination of odd and even image fields
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

An active pixel sensor includes mixed analog and digital signal integration on the same substrate. The analog part of the array forms the active pixel sensor, and the digital part of the array does digital integration of the signal.

Claims

1-8. -8. (canceled)

9. A method of operating a CMOS imager sensor, the method comprising:

exposing an array of active pixels of the CMOS image sensor to an image;

reading out a first group of pixel analog signals from the array of pixels, while the pixels continue to generate charge from the exposure to the image, to generate a first group of circuitry analog signals associated with a first exposure of the pixels to the image;

converting the first group of circuitry analog signals into a corresponding first group of digital signals associated with the first exposure of the pixels to the image;

storing the first group of digital signals;

reading out a second group of pixel analog signals from the array of pixels, while the pixels continue to generate charge from the exposure to the image, to generate a second group of circuitry analog signals associate with a second exposure of the pixels to the image;

converting the second group of circuitry analog signals into a corresponding second group of digital signals associated with the second exposure of the pixels to the image;

storing the second group of digital signals;

combining the first group of digital signals with the second group of digital signals to produce a final group of digital signals representing the image;

storing the final group of digital signals; and

reading out the final group of digital signals.

10. The method of claim 9, wherein the step of combining the first group with the second group comprises summing the first group with the second group.

11. The method of claim 9, wherein the converting of the first group of circuitry analog signals and the second group of circuitry analog signals comprises column-parallel analog to digital conversion.

12. The method of claim 9, further comprising performing correlated double-sampling on pixel signals from the array to produce said first and second groups of pixel analog signals.

13. The method of claim 12, wherein said first and second groups of pixel analog signals produced by the correlated double-sampling comprise pixel signals and reference signals respectfully associated with each of the pixel signals.

14. The method of claim 9, further comprising:

reading out a third group of pixel analog signals from the array of pixels, while the pixels continue to generate charge from the exposure to the image, to generate a third group of circuitry analog signals associated with a third exposure of the pixels to the image;

converting the third group of circuitry analog signals into a corresponding third group of digital signals associated with the third exposure of the pixels to the image;

storing the third group of digital signals; and

combining the third group of digital signals with the first and second groups of digital signals to produce the final group of digital signals representing the image.

15. The method of claim 9, wherein reading out the second group of pixel analog signals from the array of pixels occurs directly after reading out the first group of pixel analog signals.

16. An imager comprising:

an array of active pixels of a CMOS image sensor;

a sampling circuit for reading out a first group of pixel analog signals from the array of pixels to generate a first group of circuitry analog signals associated with a first exposure of the pixels to an image and for reading out a second group of pixel analog signals from the array of pixels to generate a second group of circuitry analog signals associated with a second exposure of the pixels to the image, wherein the sampling circuit reads out the first and second group of pixel analog signals while the pixels continue to generate charge from exposure to the image;

a converter for converting the first group of circuitry analog signals into a corresponding first group of digital signals associated with the first exposure of the pixels to the image and converting the second group of circuitry analog signals into a corresponding second group of digital signals associated with the second exposure of the pixels to the image;

a memory for storing the first and second groups of digital signals; and

a circuit for combining the first and second groups of digital signals to produce a final group of digital signals representing the image.

17. The imager of claim 16, wherein the final group of digital signals is stored in the memory.

18. The imager of claim 16, wherein the combining circuit combines the first and second groups of digital signals by summing the first group of digital signals with the second group of digital signals.

19. The imager of claim 18, wherein the final group of digital signals represents a digital integration of the array of pixels during the first and second exposures of the array of pixels to the image.

20. The imager of claim 16, wherein the sampling circuit is an analog double-sample circuit.

21. The imager of claim 20, wherein the analog double-sample circuit reads out the first group of pixel analog signals and a first group of reference signals, where each of the reference signals is respectfully associated with an analog signal.

22. The imager of claim 16, wherein the converter is a column-parallel analog to digital converter.

23. The imager of claim 16, wherein the sampling circuit reads out a third group of pixel analog signals from the array of pixels to generate a third group of circuitry analog signals associated with a third exposure of the pixels to the image while the pixels continue to generate charge from exposure to the image.

24. The imager of claim 23, wherein the converter converts the third group of circuitry analog signals into a corresponding third group of digital signals associated with the third exposure of the pixels to the image.

25. The imager of claim 24, wherein the memory stores the third group of digital signals.

26. The imager of claim 25, wherein the combining circuit combines the third group of digital signals with the first and second groups of digital signals to produce the final group of digital signals representing the image.

27. The imager of claim 16, wherein the second group of pixel analog signals from the array of pixels is readout by the sampling circuit directly after the first group of pixel analog signals from the array of pixels is readout by the sampling circuit.

28. An imager comprising:

an array of pixels disposed on a substrate;

a first analog signal processor for processing a plurality of analog signals received from a first pixel in the array of pixels during an integration period of said pixel, wherein said pixel accumulates charge during said integration period and the first pixel is sampled multiple times during the integration period and during each sampling one of the plurality of analog signals is produced, said analog processor providing each of said plurality of analog signals as processed analog signals;

a first circuit for converting each of said processed analog signals to digital signals;

a first digital signal processor for receiving and processing said digital signals; and

a first digital memory for storing said digital signals,

wherein said digital signals are accumulated by said imager, the accumulation of which represents a digital integrated value for the integration period of the first pixel.

29. The imager of claim 28, wherein the circuit for converting said processed analog signals is an oversampling converter.

30. The imager of claim 28, wherein said analog signal processor comprises a column analog double sampling circuitry, wherein said column analog double sampling circuitry comprises a sample circuit for a pixel signal and a sample circuit for a reference signal from said pixel.

31. The imager of claim 28, further comprising:

a second analog signal processor for processing a plurality of analog signals generated by a second pixel in the array during an integration period for the second pixel;

a second circuit for converting said processed analog signals from said second analog processor to digital signals; and

a second digital processor for receiving and processing said digital signals from said second circuit.

32. The imager of claim 31, further comprising a second digital memory for storing digital signals from the second digital processor, wherein said first and second digital memories are respectively located on first and second sides of the array of pixels.

33. The imager of claim 28, wherein said first pixel is sufficiently small so that it lacks sufficient capacity to integrate incoming photons for the entirety of said integration period.

34. The imager of claim 28, wherein said first analog signal processor comprises at least one preamplifier with adjustable gain.

35. A method of operating an imager comprising:

capturing an image with a pixel sensor array during an integration period in which pixels in the array accumulate charge;

causing said pixels in the array to each produce electrical signals representing said image;

sampling said electrical signals for each pixel multiple times during said integration period;

converting after every sampling said electrical signals for each pixel to digital signals; and

accumulating and storing said digital signals for each pixel, said accumulated digital signals for each pixel representing a digital integrated signal for said integration period.

36. The method of claim 35, further comprising outputting said integrated signal for each pixel.

37. The method of claim 35, wherein said digital signals for each pixel comprise at least one of each of a light intensity signal and a reference signal.

38. The method of claim 35, wherein at least a first set of said electrical signals is accumulated and stored in a first memory and at least a second set of electrical signals is accumulated and stored in a second memory.

39. The method of claim 38, wherein the act of converting said first set of electrical signals is performed by a first analog to digital converter and the act of converting said second set of electrical signals is performed by a second analog to digital converter.

40. The method of claim 39, further comprising outputting at least one integrated signal from each of said first and second memories.

41. An imager circuit comprising:

an active pixel image sensor array;

at least one circuit for sampling and converting analog information from a plurality of pixels in said array to digital values;

at least one digital memory for storing and accumulating said digital values, wherein said plurality of pixels in said active pixel image sensor array are sampled multiple times during an integration period in which said plurality of pixels accumulate charge and each sampled value is stored and accumulated in said at least one digital memory, said accumulated values representing a respective integrated signal for each pixel during said integration period; and

a controller for controlling the sampling of analog information from said pixels and said storage of digital values in said at least one digital memory.

42. The imager circuit of claim 41, further comprising at least one analog signal processor electrically connected to receive said analog information from said image sensor array and to provide said information to said at least one analog to digital converter.

43. The imager circuit of claim 42, wherein said at least one analog signal processor comprises either at least one preamplifier with adjustable gain or column analog double sampling circuitry.

44. The imager circuit of claim 41, wherein said at least one digital memory comprises first and second digital memories.

45. The imager circuit of claim 44, wherein said first and second digital memories are respectively located on first and second opposite sides of said image sensor array.

46. The imager circuit of claim 44, further comprising first and second digital signal processors for providing respective first and second sets of digital values to said first and second digital memories.

47. An imager comprising:

an array of pixels disposed on a substrate;

a first column analog double sampling circuitry for processing a plurality of analog signals received from a first pixel in the array of pixels during an integration period of said first pixel, wherein the first pixel is sampled multiple times during the integration period and during each sampling one of the plurality of analog signals is produced;

a first converter for converting each of said processed analog signals from said first column analog double sampling circuitry to digital signals;

a first digital signal processor for receiving and processing said digital signals; and

a first digital memory for storing said digital signals,

wherein said digital signals stored in said first digital memory are accumulated by said imager, the accumulation of which represents a digital integrated value for the integration period of the first pixel.

48. The imager of claim 47, further comprising:

a second column analog double sampling circuitry for processing a plurality of analog signals received from a second pixel in the array of pixels during an integration period of said second pixel;

a second converter for converting said processed analog signals from said second column analog double sampling circuitry to digital signals;

a second digital signal processor for receiving and processing said digital signals; and

a second digital memory for storing said digital signals,

wherein said digital signals stored in said second digital memory are accumulated by said imager, the accumulation of which represents a digital integrated value for the integration period of the second pixel.