Refresh Circuitry for Phase Change Memory

• US 20110116309A1
• Filed: 01/21/2011
• Published: 05/19/2011
• Est. Priority Date: 07/15/2009
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lung, Hsiang-Lan
• Granted Patent: US 8,228,721 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step

Abstract

A memory device as described herein includes a reference array of phase change memory cells and a memory array of phase change memory cells, where a difference between a current data set stored in the reference array and an expected data set is used to determine when to refresh the memory array. The high resistance state for the reference array is a “partial reset” state having a minimum resistance less than that of the high resistance state for the memory array. Sense circuitry is adapted to read the memory cells of the reference array and to generate a refresh command signal if there is a difference between a current data set stored in the reference array and an expected data set, and control circuitry responsive to the refresh command signal to perform a refresh operation on the memory cells of the memory array.

Claims

1. A memory device comprising:

an array of memory cells;

sense circuitry to read a current data set from a plurality of the memory cells of the array of memory cells; and

control circuitry to perform a refresh operation on the array of memory cells if there is a difference between the current data set read by the sense circuitry and an expected data set.

2. The memory device according to claim 1, wherein the memory cells are phase change memory cells.

3. The memory device according to claim 1, wherein the array of memory cells comprises a memory array of memory cells and a reference array of memory cells.

4. The memory device according to claim 3, wherein the control circuitry performs a refresh operation on both the memory array and the reference array of memory cells.

5. The memory device according to claim 3, further comprising bias circuitry to establish low and high resistance states in the memory array and in the reference array, the high resistance state for the reference array having a minimum resistance less than that of the high resistance state for the memory array.

6. The memory device according to claim 5, wherein the bias circuitry is adapted to apply a first pulse to a memory cell in the reference array to establish the high resistance state of the reference array, and is adapted to apply a second pulse to a memory cell in the memory array to establish the high resistance state of the memory array, the first and second pulses having different values for at least one of pulse width and pulse height.

7. The memory device according to claim 5, wherein the low resistance states of the memory cells in the reference array and of the memory cells in the memory array correspond to the same resistance range.

8. The memory device according to claim 3, wherein memory cells in the reference array and memory cells in the memory array respectively comprise memory elements having different physical configurations.

9. The memory device according to claim 3, wherein memory cells in the reference array and memory cells in the memory array respectively comprise memory elements having the same physical configuration.

10. The memory device according to claim 3, memory cells in the reference array have a smaller active region than that of memory cells in the memory array.

11. The memory device according to claim 1, wherein the sense circuitry reads out the current data set from said plurality of the memory cells.

12. The memory device according to claim 1, wherein the sense circuitry reads said plurality of the memory cells and generates a refresh command signal if there is a difference between the current data set and the expected data set.

13. The memory device according to claim 12, further comprising memory adapted to store a first checksum corresponding to the expected data set, and wherein the sense circuitry includes logic to compute a second checksum using the current data set, and to compare the first and second checksums to generate the refresh command signal.

14. The memory device according to claim 1, wherein the expected data set is stored in said plurality of the memory cells and is a checkerboard pattern of alternating high and low resistance states among adjacent memory cells in said plurality of the memory cells.

15. The memory device according to claim 1, wherein said plurality of the memory cells includes 100 or more memory cells.

16. A method for operating a memory device comprising an array of memory cells, the method comprising:

reading the array of memory cells;

determining a difference between a current data set from a plurality of the memory cells of the array of memory cells and an expected data set; and

upon determination of the difference, performing a refresh operation on the array of memory cells.

17. The method according to claim 16, wherein the array of memory cells comprises an array of phase change memory cells.

18. The method according to claim 16, wherein said determining includes:

computing a checksum using the current data set; and

comparing the checksum and an expected checksum to determine the difference.

19. The method according to claim 16, wherein the array of memory cells comprises a memory array of memory cells and a reference array of memory cells.

20. The method according to claim 19, further comprising storing low and high resistance states in the memory array and in the reference array, the high resistance state for the reference array having a minimum resistance less than that of the high resistance state for the memory array.

21. The method according to claim 20, wherein said storing includes:

applying a first pulse to a memory cell in the reference array to establish the high resistance state of the reference array; and

applying a second pulse to a memory cell in the memory array to establish the high resistance state of the memory array, the first and second pulses having different values for at least one of pulse width and pulse height.

22. The method according to claim 20, wherein the low resistance states of the reference array and the memory array correspond to the same resistance range.

23. The method according to claim 16, wherein:

the reading step comprises reading said plurality of the memory cells; and

the difference determining step is carried out by determining a difference between the current data set stored in said plurality of the memory cells and the expected data set.