TWO-WIRE ANALOG FET-BASED DIMMER SWITCH

• US 20110121812A1
• Filed: 11/23/2010
• Published: 05/26/2011
• Est. Priority Date: 11/25/2009
• Status: Active Grant

• Current Assignee: Lutron Technology Company LLC
• Original Assignee: Lutron Electronics Company Incorporated (Lutron Electronics)
• Inventors: Salvestrini, Christopher James
• Granted Patent: US 8,729,814 B2
• Time in Patent Office: Days
• US Class Current: 323/323
• CPC Class Codes: H05B 39/04 Controlling
• CPC Class Codes: H05B 39/048 with reverse phase control
• CPC Class Codes: Y02B 20/00 Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps

Abstract

A two-wire load control device, such as, a dimmer switch, for controlling the amount of power delivered from an AC power source to an electrical load comprise a bidirectional semiconductor switch having first and second anti-series connected switching transistors (such as, for example, field-effect transistors) that are adapted to be coupled between the source and the load, and are controlled to be conductive and non-conductive in a complementary basis. The bidirectional semiconductor switch is operable to be rendered conductive and to remain conductive independent of the magnitude of a load current conducted through semiconductor switch. The dimmer switch also comprises a drive circuit for rendering the first and second switching transistors conductive and non-conductive each half-cycle on the complementary basis, so as to control the amount of power delivered to the electrical load to a desired amount of power.

Claims

1. A load control device for controlling the amount of power delivered from an AC power source to an electrical load, the load control device comprising:

a bidirectional semiconductor switch adapted to be coupled in series electrical connection between the AC power source and the electrical load for conducting a load current from the AC power source to the electrical load, the bidirectional semiconductor switch comprising first and second switching transistors coupled in anti-series connection, the first and second switching transistors each operable to be rendered conductive and to remain conductive independent of the magnitude of the load current conducted through the semiconductor switch; and

a drive circuit for rendering the first and second switching transistors conductive and non-conductive each half-cycle, so as to control the amount of power delivered to the electrical load to the desired amount;

wherein the drive circuit controls the first and second switching transistors on a complementary basis.

2. The load control device of claim 1, further comprising:

an analog control circuit for generating a timing voltage representative of a desired amount of power to be delivered to the electrical load;

wherein the drive circuit receives the timing voltage and rendering the bidirectional semiconductor switch conductive and non-conductive each half-cycle in response to the timing voltage.

3. The load control device of claim 2, wherein the first and second switching transistors comprise first and second FETs, respectively.

4. The load control device of claim 3, wherein the drive circuit renders the first FET conductive during the positive half-cycles and the second FET conductive during the negative half-cycles using forward phase-control dimming.

5. The load control device of claim 4, wherein the drive circuit comprises a first SR latch having an output coupled to the gate of the first FET and a second SR latch having an output coupled to the gate of the second FET;

and

wherein the set input of the first SR latch is coupled to the reset input of the second SR latch, and the set input of the second SR latch is coupled to the reset input of the first SR latch, such that the FETs are rendered conductive in the complementary basis.

6. The load control device of claim 5, further comprising:

an overcurrent protection circuit including a sense resistor coupled in series with the first and second FETs and operable to generate a voltage having a magnitude representative of the magnitude of the load current, the overcurrent protection circuit operatively coupled to the first and second FETs for rendering the FETs non-conductive in the event of an overcurrent condition in the FETs.

7. The load control device of claim 6, wherein the drive circuit comprises a third SR latch having an output operatively coupled to the first FET for rendering the first FET non-conductive, and a fourth SR latch having an output operatively coupled to the second FET for rendering the second FET non-conductive, the overcurrent protection circuit coupled to the set input of the third SR latch for rendering the first FET non-conductive in the event of an overcurrent condition in the positive half-cycles, the overcurrent protection circuit further coupled to the set input of the fourth SR latch for rendering the second FET non-conductive in the event of an overcurrent condition in the negative half-cycles.

8. The load control device of claim 7, wherein the reset input of the third SR latch is coupled to the set input of the second SR latch, such that the third SR latch stops rendering the first FET non-conductive when the second FET is rendered conductive during the next negative half-cycle;

and

wherein the reset input of the fourth SR latch is coupled to the set input of the first SR latch, such that the fourth SR latch stops rendering the second FET non-conductive when the second FET is rendered conductive during the next positive half-cycle.

9. The load control device of claim 5, wherein the drive circuit further comprises a triggering circuit operable to conduct a pulse of current in response to the timing voltage, the drive circuit further comprising a first optocoupler having an input photodiode operable to conduct the pulse of current of the triggering circuit during the positive half-cycles, and a second optocoupler having an input photodiode operable to conduct the pulse of current of the triggering circuit during the negative half-cycles.

10. The load control device of claim 9, wherein the first optocoupler has an output coupled to the set input of the first SR latch and to the reset input of the second SR latch for rendering the first FET conductive and the second FET non-conductive during the positive half-cycles, the second optocoupler having an output coupled to the set input of the second SR latch and the reset input of the first SR latch for rendering the second FET conductive and the first FET non-conductive during the negative half-cycles.

11. The load control device of claim 5, further comprising:

a power supply for generating a DC supply voltage for powering the first and second SR latches.

12. The load control device of claim 11, wherein the power supply comprises a pass-transistor circuit followed by a snap-on circuit.

13. The load control device of claim 4, wherein the drive circuit comprises a first capacitor coupled to a control input of the first FET for rendering the FET conductive during the positive half-cycles, and a second capacitor coupled to a control input of the second FET for rendering the FET conductive during the negative half-cycles.

14. The load control device of claim 13, wherein the drive circuit comprises a first pulse transformer having a secondary winding coupled to the first capacitor, a second pulse transformer having a secondary winding coupled to the second capacitor, and a triggering circuit coupled in series with primary windings of the first and second pulse transformers, the triggering circuit operable to conduct a pulse of current through the primary windings of the pulse transformers in response to the timing voltage for charging the first capacitor during the positive half-cycles and the second capacitor during the negative half-cycles.

15. The load control device of claim 14, wherein the voltage across the first capacitor is controlled to approximately zero volts to render the first FET non-conductive at approximately the same time that the second capacitor charges from the secondary winding of the second pulse transformer to render the second FET conductive during the negative half-cycles;

and

the voltage across the second capacitor is controlled to approximately zero volts to render the second FET non-conductive at approximately the same time that the first capacitor charges from the secondary winding of the first pulse transformer to render the first FET conductive during the positive half-cycles.

16. The load control device of claim 15, wherein the drive circuit comprises a first zener diode coupled in series between the secondary winding of the first pulse transformer and the first capacitor, such that the first zener diode forward-biased during the positive half-cycles for charging the first capacitor and reverse-biased during the negative half-cycles for driving the voltage across the first capacitor to approximately zero volts.

17. The load control device of claim 14, wherein the first and second pulse transformers comprise a single pulse transformer having a single primary winding coupled in series with the triggering circuit.

18. The load control device of claim 17, wherein the single pulse transformer has a secondary winding having a center tap connection.

19. The load control device of claim 13, wherein the drive circuit comprises a diac and a pulse transformer having a single primary winding coupled in series with the diac, the pulse transformer further comprising a secondary winding having a center tap connection, the first capacitor operatively coupled between the center tap connection and a first end of the secondary winding, the second capacitor operatively coupled between the center tap connection and a second end of the secondary winding, the diac operable to conduct a pulse of current through the primary winding of the pulse transformer in response to the timing voltage for charging the first capacitor during the positive half-cycles and the second capacitor during the negative half-cycles.

20. The load control device of claim 13, wherein the drive circuit is characterized as having inherent shorted-FET protection, such that the first FET is rendered conductive at all times if the second FET has failed shorted, and vice versa.

21. The load control device of claim 2, wherein the analog control circuit comprises a timing circuit and the timing voltage increases at a rate that is representative of the desired amount of power to be delivered to the load.

22. The load control device of claim 21, wherein the timing circuit is coupled in parallel with the bidirectional semiconductor switch and is configured so as to conduct a timing current through the load.

23. The load control device of claim 22, wherein the drive circuit comprises a capacitor operable to charge from the AC power source through a potentiometer for generating the timing voltage across the capacitor, such that the timing voltage is responsive to the resistance of the potentiometer.

24. The load control device of claim 1, wherein the first FET is rendered conductive and the second FET is rendered non-conductive at substantially the same time during the positive half-cycles, and the first FET is rendered non-conductive and the second FET is rendered conductive at substantially the same time during the negative half-cycles.

25. A two-wire load control device for controlling the amount of power delivered from an AC power source to an electrical load, the load control device comprising:

a bidirectional semiconductor switch adapted to be coupled in series electrical connection between the AC power source and the electrical load for conducting a load current from the AC power source to the electrical load, the bidirectional semiconductor switch comprising first and second switching transistors coupled in anti-series connection, the first and second switching transistors each operable to be rendered conductive and to remain conductive independent of the magnitude of the load current conducted through semiconductor switch;

an analog control circuit for generating a timing voltage representative of a desired amount of power to be delivered to the electrical load, the analog control circuit coupled so as to conduct a timing current through the electrical load; and

a drive circuit for receiving the timing voltage and independently rendering the first and second switching transistors conductive and non-conductive each half-cycle in response to the timing voltage.

26. The load control device of claim 25, wherein the first and second switching transistors comprises first and second FETs, respectively.

27. The load control device of claim 26, wherein the drive circuit renders the first FET conductive during the positive half-cycles and the second FET conductive during the negative half-cycles using forward phase-control dimming.

28. The load control device of claim 27, wherein the drive circuit comprises a first SR latch having an output coupled to the gate of the first FET and a second SR latch having an output coupled to the gate of the second FET;

and

wherein the set input of the first SR latch is coupled to the reset input of the second SR latch, and the set input of the second SR latch is coupled to the reset input of the first SR latch, such that the FETs are rendered conductive in a complementary manner.

29. The load control device of claim 27, wherein the drive circuit comprises a first capacitor coupled to a control input of the first FET for rendering the FET conductive during the positive half-cycles, and a second capacitor coupled to a control input of the second FET for rendering the FET conductive during the negative half-cycles, the drive circuit further comprising a first pulse transformer having a secondary winding coupled to the first capacitor, a second pulse transformer having a secondary winding coupled to the second capacitor, and a triggering circuit coupled in series with primary windings of the first and second pulse transformers, the triggering circuit operable to conduct a pulse of current through the primary windings of the pulse transformers in response to the timing voltage for charging the first capacitor during the positive half-cycles and the second capacitor during the negative half-cycles.

30. The load control device of claim 27, wherein the drive circuit comprises a diac and a pulse transformer having a single primary winding coupled in series with the diac, the pulse transformer further comprising a secondary winding having a center tap connection, the first capacitor operatively coupled between the center tap connection and a first end of the secondary winding, the second capacitor operatively coupled between the center tap connection and a second end of the secondary winding, the diac operable to conduct a pulse of current through the primary winding of the pulse transformer in response to the timing voltage for charging the first capacitor during the positive half-cycles and the second capacitor during the negative half-cycles.

31. The load control device of claim 27, wherein the drive circuit is characterized as having inherent shorted-FET protection, such that the first FET is rendered conductive at all times if the second FET has failed shorted, and vice versa.

32. The load control device of claim 25, wherein the analog control circuit comprises a timing circuit and the timing voltage increases at a rate that is representative of the desired amount of power to be delivered to the load.

33. The load control device of claim 32, wherein the timing circuit is coupled in parallel with the bidirectional semiconductor switch and is configured so as to conduct a timing current through the load.

34. The load control device of claim 33, wherein the drive circuit comprises a capacitor operable to charge from the AC power source through a potentiometer for generating the timing voltage across the capacitor, such that the timing voltage is responsive to the resistance of the potentiometer.

35. The load control device of claim 25, wherein the first FET is rendered conductive and the second FET is rendered non-conductive at substantially the same time during the positive half-cycles, and the first FET is rendered non-conductive and the second FET is rendered conductive at substantially the same time during the negative half-cycles.

36. The load control device of claim 25, wherein the drive circuit controls the first and second FETs on a complementary basis, such that at least one of the FETs is conductive at all times.

37. A gate drive circuit for driving first and second anti-series-connected switching transistors in a load control device for controlling the amount of power delivered from an AC power source to an electrical load, the gate drive circuit configured for receipt of a timing voltage representative of a desired amount of power to be delivered to the electrical load, the gate drive circuit adapted to be coupled to control inputs of the switching transistors for controlling the switching transistors to be conductive and non-conductive in response to the timing voltage, the gate drive circuit comprising:

a first capacitor adapted to be coupled to the control input of the first switching transistor for rendering the switching transistor conductive during the positive half-cycles of the AC power source;

a second capacitor adapted to be coupled to the control input of the second switching transistor for rendering the switching transistor conductive during the negative half-cycles of the AC power source;

a first pulse transformer having a secondary winding operatively coupled to the first capacitor;

a second pulse transformer having a secondary winding operatively coupled to the second capacitor; and

a triggering circuit coupled in series with primary windings of the first and second pulse transformers, the triggering circuit operable to conduct a pulse of current through the primary windings of the pulse transformers in response to the timing voltage for charging the first capacitor during the positive half-cycles and the second capacitor during the negative half-cycles, such that the drive circuit is operable to render the first and second switching transistors conductive and non-conductive each half-cycle for controlling the amount of power delivered to the electrical load to the desired amount.

38. The gate drive circuit of claim 37, wherein the drive circuit controls the first and second switching transistors on a complementary basis, such that at least one of the switching transistors is conductive at all times.

39. The gate drive circuit of claim 37, wherein the first and second pulse transformers comprise a single pulse transformer having a single primary winding coupled in series with the triggering circuit, and a secondary winding having a center tap connection.

40. A gate drive circuit for driving first and second anti-series-connected switching transistors in a load control device for controlling the amount of power delivered from an AC power source to an electrical load, the gate drive circuit configured for receipt of a timing voltage representative of a desired amount of power to be delivered to the electrical load, the gate drive circuit adapted to be coupled to control inputs of the switching transistors for controlling the switching transistors to be conductive and non-conductive in response to the timing voltage, the gate drive circuit comprising:

a triggering circuit operable to conduct a pulse of current in response to the timing voltage;

a first optocoupler having an input photodiode operable to conduct the pulse of current of the triggering circuit during the positive half-cycles of the AC power source;

a second optocoupler having an input photodiode operable to conduct the pulse of current of the triggering circuit during the negative half-cycles;

a first SR latch having a set input coupled to an output of the first optocoupler, the first SR latch further comprising an output coupled to the gate of the first switching transistor for rendering the first switching transistor conductive during the positive half-cycles; and

a second SR latch having a set input coupled to an output of the second optocoupler, the second SR latch further comprising an output coupled to the gate of the second switching transistor for rendering the second switching transistor conductive during the negative half-cycles;

wherein the reset input of the first SR latch is coupled to the set input of the second SR latch, and the reset input of the second SR latch is coupled to the set input of the first SR latch, such that the switching transistors are rendered conductive in the complementary basis.

41. A load control circuit for coupling in series between an AC source voltage and a load device comprising:

a controllable bidirectional switch for coupling selected portions of positive and negative half-cycles of the AC source voltage to the load device;

a timing circuit coupled to the AC source voltage for producing a timing signal; and

a gate drive circuit receiving the timing signal and producing separate first and second drive signals for causing the bidirectional switch to be conductive for the selected portions of the positive and negative half-cycles, respectively, thereby to provide current to the load device from the AC voltage source during the selected portions of the respective positive and negative half-cycles;

wherein the gate drive circuit produces the first drive signal during the positive half-cycle and the second drive signal during the negative half-cycle.

42. The load control circuit of claim 41, wherein the first drive signal is generated by a first pulse transformer and the second drive signal is generated by a second pulse transformer and wherein the first and second pulse transformers have series-connected primaries connected to receive the timing signal.

43. The load control circuit of claim 42, wherein the first pulse transformer has a secondary coupled to charge a first capacitor through a first diode for producing the first drive signal during the positive half-cycle, the first capacitor discharging during the negative half-cycle to below a threshold voltage for keeping the bidirectional switch conductive.

44. The load control circuit of claim 43, wherein the second pulse transformer has a secondary coupled to charge a second capacitor through a second diode for producing the second drive signal during the negative half-cycle, the second capacitor discharging during the positive half-cycle to below a threshold voltage for keeping the bidirectional switch conductive.

45. The load control circuit of claim 44, wherein the bidirectional switch comprises first and second anti-series connected FETs, and wherein the first FET has a gate receiving the first drive signal and the second FET has a gate receiving the second drive signal, both FETs having respective channel regions, and wherein when the first FET is rendered conductive by the first drive signal, the second FET is provided with the second drive signal that renders the channel region of the second FET non-conductive, said second FET having a body diode through which the positive half-cycle flows;

further wherein when the second FET is rendered conductive by the second drive signal, the first FET is provided with the first drive signal that renders the channel region of the first FET non-conductive, said first FET having a body diode through which the negative half-cycle flows.

46. The load control circuit of claim 45, wherein the load control circuit is inherently protected against an asymmetric voltage being provided to the load device in the event of a short circuit failure in one of said two FETs by driving the non-failing FET into full conduction.

47. The load control circuit of claim 44, wherein the second diode is a second zener diode and the second capacitor discharges through the second zener diode during the positive half-cycle.

48. The load control circuit of claim 43, wherein the first diode is a first zener diode and the first capacitor discharges through the first zener diode during the negative half-cycle.

49. The load control circuit of claim 42, further comprising an overcurrent protection circuit monitoring current in said bidirectional switch and turning off said bidirectional switch if the current exceeds an overcurrent threshold.

50. The load control circuit of claim 49, wherein the overcurrent protection circuit comprises a sense resistor in series with the bidirectional switch and a first transistor coupled to the sense resistor for turning off said first drive signal during the positive half-cycle and a second transistor coupled to said sense resistor for turning off the second drive signal during the negative half-cycle.

51. The load control circuit of claim 41, wherein the timing circuit comprises an RC circuit, with at least one resistive element comprising a variable resistor for setting a charging rate of a capacitor of the RC circuit and for determining timing of said timing signal.

52. The load control circuit of claim 51, wherein the timing circuit comprises a voltage compensation element for maintaining the charging rate of said capacitor constant when the AC source voltage varies.

53. The load control circuit of claim 52, wherein the voltage compensation element comprises a component having an inverse voltage-current characteristic such that when the current through the component decreases, the voltage across the component increases and vice versa, thereby affecting the charging rate of said capacitor.

54. The load control circuit of claim 53, wherein the component comprises a DIAC coupled across a portion of a resistance of said RC circuit and said capacitor.

55. The load control circuit of claim 41, wherein the load control circuit is a dimmer circuit and the load device comprises a lighting load.

56. The load control circuit of claim 55, wherein the lighting load comprises an LED driver driving the LED light source.

57. The load control circuit of claim 55, wherein the lighting load comprises an electronic dimming ballast driving a fluorescent lamp.

58. The load control circuit of claim 41, further comprising a voltage threshold device provided to couple the timing signal to the gate drive circuit, the voltage threshold device triggering to conduct the timing signal at a predetermined voltage level.

59. The load control circuit of claim 58, wherein the voltage threshold device comprises a diac.

60. The load control circuit of claim 41, wherein the selected portions of the positive and negative half-cycles of the AC source voltage comprises forward phase control selected portions.