Methods of Forming Field Effect Transistors, Methods of Forming Field Effect Transistor Gates, Methods of Forming Integrated Circuitry Comprising a Transistor Gate Array and Circuitry Peripheral to the Gate Array, and Methods of Forming Integrated Circuitry Comprising a Transistor Gate Array Including First Gates and Second Grounded Isolation Gates

• US 20110124168A1
• Filed: 01/31/2011
• Published: 05/26/2011
• Est. Priority Date: 02/02/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kim, Young Pil, Parekh, Kunal R.
• Granted Patent: US 8,389,363 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated.

Claims

1. A method of forming a field effect transistor, comprising:

forming masking material over semiconductive material of a substrate;

forming a trench through the masking material and into the semiconductive material;

forming gate dielectric material within the trench in the semiconductive material;

depositing gate material within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material;

recessing the gate material to have a planar outermost surface received within the trench in the masking material, the planar outermost surface spanning completely across the trench in the masking material; and

forming source/drain regions.

4. The method of claim 1 wherein the depositing of the gate material at least fills the trench in the masking material and the trench in the semiconductive material with the gate material.

5. The method of claim 1 wherein the depositing of the gate material overfills the trench in the masking material and the trench in the semiconductive material with the gate material.

7. The method of claim 1 comprising removing at least a majority of the masking material after depositing the gate material.

8. The method of claim 1 being void of photolithographic patterning of the gate material after its deposition.

9. The method of claim 1 wherein depositing the gate material covers the masking material with the gate material, and comprising removing the gate material selectively relative to and exposing the masking material effective to isolate the gate material within the trench in the masking material and the trench in the semiconductive material.

2-3. -3. (canceled)

6. (canceled)

10-33. -33. (canceled)

34. A method of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, comprising:

forming masking material over semiconductive material of a substrate;

forming array circuitry trenches through the masking material and into the semiconductive material;

depositing array gate material within the array circuitry trenches in the masking material and within the array circuitry trenches in the semiconductive material;

after depositing the array gate material, forming peripheral circuitry trenches through the masking material;

depositing peripheral circuitry gate material within the peripheral circuitry trenches within the masking material;

the array circuitry trenches being formed using a masking step, and further comprising forming grounded gate trenches through the masking material in the array in the same masking step in which the array circuitry trenches are formed, the grounded gate trenches being formed into trench isolation material received within the substrate semiconductive material.

36-84. -84. (canceled)

85. A method of forming a field effect transistor, comprising:

forming masking material over semiconductive material of a substrate, the masking material having a thickness expanse over the semiconductive material;

forming a trench through the masking material and into the semiconductive material;

forming gate dielectric material within the trench in the semiconductive material;

depositing gate material within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material;

recessing the gate material to have an outermost surface spanning completely across the trench in the masking material and that is everywhere received within the trench within the thickness expanse of the masking material and everywhere outward of the semiconductive material into which the trench was formed; and

forming source/drain regions.

86. The method of claim 85 comprising removing at least a majority of the masking material after the recessing.

87. A method of forming a field effect transistor, comprising:

forming masking material over semiconductive material of a substrate;

forming a trench through the masking material and into the semiconductive material;

forming gate dielectric material within the trench in the semiconductive material;

providing gate material within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material;

exposing sidewalls of the gate material outward of the semiconductive material;

forming insulative material over the sidewalls of the gate material outward of the semiconductive material;

anisotropically etching the insulative material to form insulative sidewall spacers over the sidewalls of the gate material outward of the semiconductive material; and

forming source/drain regions.

88. The method of claim 87 comprising forming the gate material to comprise higher electrically conductive material received over lower electrically conductive material, said exposing of sidewalls of the gate material only being of sidewalls of the higher electrically conductive material.

89. The method of claim 87 comprising forming the gate material to comprise higher electrically conductive material received over lower electrically conductive material, the anisotropically etched sidewall spacers being formed over sidewalls of the higher electrically conductive material.

90. The method of claim 89 wherein the anisotropically etched sidewall spacers are not formed over sidewalls of the lower electrically conductive material.

91. The method of claim 87 wherein the exposing comprises removing only some of the masking material.

92. The method of claim 91 wherein the removing is of an outer layer of one composition selectively relative to an immediately adjacent inner layer of different composition from the one.

93. The method of claim 87 comprising capping the gate material with insulating material prior to said exposing.

94. The method of claim 93 comprising forming the anisotropically etched sidewall spacers over sidewalls of the insulating material.

95. The method of claim 87 comprising:

forming the gate material to comprise higher electrically conductive material received over lower electrically conductive material, the anisotropically etched sidewall spacers being formed over sidewalls of the higher electrically conductive material;

capping the gate material with insulating material prior to said exposing; and

forming the anisotropically etched sidewall spacers over sidewalls of the insulating material.

96. The method of claim 87 wherein the anisotropically etched sidewall spacers are formed outward of a portion of the masking material.

97. The method of claim 87 wherein the anisotropically etched sidewall spacers are formed outward of a portion of the masking material that remains as part of a finished construction of integrated circuitry incorporating the field effect transistor.

98. The method of claim 87 wherein the anisotropically etched sidewall spacers are formed outward of an insulating layer received elevationally atop the semiconductive material.

99. A method of forming a field effect transistor, comprising:

providing gate material within and projecting outwardly of a trench in semiconductive material, the projecting gate material comprising opposing sidewalls outward of the semiconductive material;

providing gate dielectric over the gate material that is within the semiconductive material;

forming insulative material over the sidewalls of the gate material outward of the semiconductive material;

anisotropically etching the insulative material to form insulative sidewall spacers over the sidewalls of the gate material outward of the semiconductive material; and

forming source/drain regions.

100. The method of claim 99 comprising capping the gate material with insulating material prior to said etching.

101. The method of claim 100 comprising forming the anisotropically etched sidewall spacers over sidewalls of the insulating material.

102. The method of claim 99 wherein the anisotropically etched sidewall spacers are formed outward of an insulating layer received elevationally atop the semiconductive material.

103. A method of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, comprising:

forming masking material over semiconductive material of a substrate;

in a first masking step, forming array circuitry trenches through the masking material and into the semiconductive material and forming a first peripheral circuitry trench through the masking material;

depositing first gate material within the array circuitry trenches and the first peripheral circuitry trench;

in a second masking step, forming a grounded gate trench through the first gate material and the masking material within array area and forming a second peripheral circuitry trench through the first gate material and the masking material within area peripheral to the array area; and

depositing second gate material within the grounded gate trench and within the second peripheral circuitry trench.

104. A method of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, comprising:

forming masking material over semiconductive material of a substrate;

in a first masking step, forming array circuitry trenches through the masking material and into the semiconductive material;

depositing first gate material within the array circuitry trenches;

in a second masking step, forming a grounded gate trench through the first gate material and the masking material within array area and forming a first peripheral circuitry trench through the first gate material and the masking material within area peripheral to the array area;

depositing second gate material within the grounded gate trench and within the first peripheral circuitry trench;

in a third masking step, forming a second peripheral circuitry trench through the second gate material and through the first gate material within the peripheral area; and

depositing third gate material within the second peripheral circuitry trench.

105. The method of claim 104 wherein no trench is formed in the peripheral area using the first masking step.