ARRAYS OF TRANSISTORS WITH BACK CONTROL GATES BURIED BENEATH THE INSULATING FILM OF A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE

• US 20110133776A1
• Filed: 12/06/2010
• Published: 06/09/2011
• Est. Priority Date: 12/08/2009
• Status: Active Grant

• Current Assignee: Soitec S.A.
• Original Assignee: Soitec S.A.
• Inventors: Mazure, Carlos, Ferrant, Richard
• Granted Patent: US 8,384,425 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate and including an array of patterns, each pattern being formed by at least one field-effect transistor, each FET transistor having, in the thin film, a source region, a drain region, a channel region, and a front control gate region formed above the channel region. The provided device further includes at least one FET transistor having a pattern including a back control gate region formed in the base substrate beneath the channel region, the back gate region being capable of being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor or to force the transistor to remain off or on whatever the voltage applied on its front control gate. This invention also provides methods of operating such semiconductor device structures.

Claims

1. A semiconductor device structure formed on a semiconductor-on-insulator substrate, with the semiconductor-on-insulator substrate comprising a thin film of semiconductor material separated from a base substrate by an insulating film, and the device structure comprising an array of patterns, with each pattern formed by at least one field-effect transistor with each such field-effect transistor having, in the thin film of the substrate, a source region, a drain region, a channel region which is delimited by the source and drain regions, and a front control gate region formed above the channel region;

wherein the patterns of the array are arranged in rows, with the source and drain regions of any one row having the same dimensions and being spaced apart by front control gate regions of a fixed dimension, and

wherein at least one such field-effect transistor of at least one pattern includes a back control gate region formed in the base substrate beneath the channel region, with the back gate region being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor.

2. The device structure of claim 1, wherein the back gate region is biased in order to force the transistor to remain off or on whatever the voltage applied on its front control gate.

3. The device structure of claim 1, wherein a plurality of the patterns in at least one row are formed on a single active zone of the thin semiconductor film of the semiconductor substrate, and wherein an isolation region delimits the adjacent patterns, the isolation region comprising a front isolation gate formed above the active zone and a back isolation gate formed in the base substrate beneath the active zone.

4. The device structure of claim 3, wherein a back isolation line connects the back isolation gates of each of the isolation regions of at least one row.

5. The device structure of claim 3, wherein a back isolation line connects the back isolation gates of each of the isolation regions of a plurality of rows.

6. The device structure of claim 3, wherein the back isolation gate has a conductivity of opposite type to that of the active zone.

7. The device structure of claim 1, wherein a back gate line connects the back gate regions of one or more transistors.

8. The device structure of claim 7, wherein a back gate line connects the back gate regions to ground or to a nominal supply voltage.

9. The device structure of claim 7, wherein a back gate line connects the back gate regions to an analog and adjustable potential.

10. The device structure of claim 1, wherein the back gate region of at least one transistor is isolated from the base substrate by a well of opposite conductivity.

11. The device structure of claim 1, wherein the back gate region of at least one transistor has a conductivity of the same type as that of the channel of that transistor.

12. The device structure of claim 1, wherein the back gate region of at least one transistor has a conductivity of opposite type to that of the channel of that transistor.

13. A method of operating a device structure according to claim 1, which comprises biasing positively or negatively at least one back control gate region in order to shift the threshold voltage of associated field-effect transistor.

14. The method of claim 13, wherein the back control gate region is biased by an analog and adjustable potential.

15. The method of claim 13, wherein the shift of the threshold voltage is sufficient to cause the associated transistor to remain off or on whatever the voltage applied to its front control gate.

16. The method of claim 13, wherein the shift of the threshold voltage is programmed by memory cells that store and deliver predetermined voltages to the at least one back control gate.

17. A re-programmable circuit comprising a device structure according to claim 1, wherein two or more adjacent rows of the pattern are interleaved with at least one further row of memory cells, and wherein the memory cells store and deliver predetermined voltages to the back control gate regions of one or both of the adjacent rows of the pattern.