DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEATH THE INSULATING LAYER

• US 20110133822A1
• Filed: 01/25/2011
• Published: 06/09/2011
• Est. Priority Date: 12/08/2009
• Status: Active Grant

• Current Assignee: Soitec S.A.
• Original Assignee: Soitec S.A.
• Inventors: Mazure, Carlos, Ferrant, Richard
• Granted Patent: US 8,508,289 B2
• Time in Patent Office: Days
• US Class Current: 327/537
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate defined by a pattern defining at least one field-effect transistor having: in the thin film of the SeOI substrate, a source region, a drain region, a channel region, and a front control gate region formed above the channel region; and in the base substrate beneath the buried oxide of the SeOI substrate, a back control gate region, arranged under the channel region and configured to shift the threshold voltage of the transistor in response to bias voltages. This invention also provides patterns defining standard-cell-type circuit structures and data-path-cell type circuit structures that include arrays of the FET patterns provided by this invention. Such circuit structures also include back gate lines connecting the back gate control regions. This invention also provides methods of operating and designing such semiconductor device structures.

Claims

1. A data-path cell fabricated on a semiconductor-on-insulator substrate comprising a surface layer of semiconductor material separated from a bulk substrate by a buried insulating layer, the cell comprising:

an array of field-effect transistors (FETs) having source, channel and drain regions formed in the surface semiconductor layer;

one or more back-control-gate regions positioned in the bulk substrate beneath the channel regions of one or more selected FETs; and

one or more back-gate lines conductively linking the back-control-gate regions to sources of selected bias voltages,

wherein the back-control-gate regions are configured so that the bias voltages modify the conductance of channel regions overlying the back-control-gate regions.

2. The data-path cell of claim 1, wherein the array comprises one or more rows of FETs, each FET row having source, channel and drain regions of the same width arranged along the row.

3. The data-path cell of claim 2, wherein the channel regions of a row have the same length separating adjacent drain and source regions.

4. The data-path cell of claim 2, wherein at least one back-gate line extends in the bulk substrate along an FET row.

5. The data-path cell of claim 2, further comprising

one or more isolation regions formed in the surface semiconductor layer and interposed between the FETs of at least one row;

and

one or more back-isolation-gate regions beneath the isolation regions in the bulk substrate;

wherein the back-gate lines further connect the back-isolation-gate regions to sources of bias voltages selected so that the isolation regions are in an OFF state in order to electrically isolate adjacent FETs on either side of that isolation region from each other.

6. The data-path cell of claim 5, wherein at least one back-isolation-gate region has conductivity of opposite type to the conductivity of the overlying isolation region.

7. The data-path cell of claim 5, wherein at least one back-gate line connects only to back-control-gate regions or only to back-isolation-gate regions, but not to both types of regions.

8. The data-path cell of claim 5, wherein a plurality of FETs with at least one interposed isolation region are in a single active zone of the surface semiconductor layer.

9. The data-path cell of claim 1, wherein at least one back-control-gate region has conductivity of opposite type to the conductivity of the overlying channel region.

10. The data-path cell of claim 1, wherein at least one back-control-gate region is isolated from the bulk substrate by a well of opposite conductivity.

11. The data-path cell of claim 1, wherein at least one back-gate line connects to a single back-control-gate region.

12. The data-path cell of claim 1, wherein at least one bias voltage is selected from a ground potential, a nominal supply voltage, and an adjustable analog potential.

13. A method of operating a data-path cell of claim 1, which comprises selecting the bias voltages to improve the performance of the data-path cell in comparison to a data-path cell of similar configuration but without back-control-gate regions.

14. The method of claim 13, wherein the improved performance comprises increased operating speed.

15. The method of claim 13, wherein the improved performance comprises reduced currents in the OFF state for one or more FETs or increased currents in the ON state for one or more FETs.

16. The method of claim 13, wherein the bias voltage of at least one back-control-gate region is varied depending on whether the overlying FET is ON or OFF.

17. A method of designing a data-path cell of claim 1 to have a determined footprint and a determined performance, with the FETs of the array being arranged in one or more rows where the FETs of a row all have source, channel and drain regions of the same width arranged along the row, wherein the method comprises:

selecting the widths of the FET rows so that the cell has no more than the determined footprint, the footprint depending at least in part on the widths of the FET rows; and

positioning back-control-gate regions beneath selected FETs and selecting the bias voltages for the provided regions so that the cell has at least the determined performance, the performance depending at least in part on the capacitances and conductance of the FETS wherein the capacitance and conductance vary with the widths of the FETs, the provided back-control-gate regions and their biases.

18. The method of claim 17, wherein, in comparison to a benchmark data-path cell having initial FET row widths but without back-gate-control regions, one or more of the following are provided:

the determined footprint is reduced and the determined performance is not reduced, or

the determined footprint is not increased and the determined performance is increased, or

the determined footprint is reduced and the determined performance is increased.

19. The method of claim 17, wherein, in comparison to a benchmark data-path cell having initial FET row widths but without back-gate-control regions, the footprint and performance requirements include one of:

the FET capacitances are reduced by up to about 33% and FET conductance are not reduced;

an operating speed is increased about 20% and the footprint is reduced about 20%;

a power consumption is reduced about 20% and the footprint is reduced about 20%; and

an operating speed is increased between about 30 and 50% and the footprint is not increased.

20. An integrated circuit comprising at plurality of the data-path cells of claim 1 arranged in one or more rows along a first direction so that, along a particular row, the output of a data-path cell connects to input of at least one succeeding data-path cell.

21. The circuit structure of claim 20, wherein the data-path cells are arranged in a plurality of rows along a first direction, and wherein the rows are arranged parallel to one another along a different second direction.