FLASH MEMORY CELL ON SeOI HAVING A SECOND CONTROL GATE BURIED UNDER THE INSULATING LAYER

• US 20110134698A1
• Filed: 11/15/2010
• Published: 06/09/2011
• Est. Priority Date: 12/08/2009
• Status: Active Grant

• Current Assignee: Soitec S.A.
• Original Assignee: Soitec S.A.
• Inventors: Mazure, Carlos, Ferrant, Richard
• Granted Patent: US 8,664,712 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

The invention relates to a flash memory cell having a FET transistor with a floating gate on a semiconductor-on-insulator (SOI) substrate composed of a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer, The transistor has in the thin film, a channel, with two control gates, a front control gate located above the floating gate and separated from it by an inter-gate dielectric, and a back control gate located within the base substrate directly under the insulating (BOX) layer and separated from the channel by only the insulating (BOX) layer. The two control gates are designed to be used in combination to perform a cell programming operation. The invention also relates to a memory array made up of a plurality of memory cells according to the first aspect of the invention, which can be in an array of rows and columns, and a method of fabricating such memory cells and memory arrays.

Claims

1. A flash memory cell comprising:

an insulating layer on a base substrate;

a thin film layer of semiconductor material on the insulating layer to form a semiconductor-on-insulator substrate;

a channel in the thin film layer, wherein the channel forms part of a field effect transistor (FET);

a gate dielectric layer on the thin film layer above the channel;

a floating gate on the gate dielectric layer;

an inter-gate dielectric layer on the floating gate;

a front control gate on the inter-gate dielectric layer above the floating gate and separated therefrom by the inter-gate dielectric; and

a back control gate within the base substrate directly under and adjacent the insulating layer.

2. The memory cell according to claim 1, wherein the back control gate extends under the entire width of the memory cell.

3. The memory cell according to claim 1, wherein the back control gate is located in such a way as to extend only facing the floating gate.

4. The memory cell according to claim 1, wherein the polarity of the back control gate is of the same type as the channel of the FET.

5. The memory cell according to claim 1, wherein the back control gate is insulated in the base substrate by a well of opposite bias.

6. The memory cell according to claim 1, wherein the insulating layer is a SiO₂ buried oxide (BOX) layer.

7. The memory cell according to claim 1, wherein the insulating layer comprises a layer of Si₃N₄ sandwiched between two layers of SiO₂.

8. The memory cell according to claim 1, which further comprises a source region and a drain region in the thin film layer.

9. The memory cell according to claim 1, wherein the channel of the FET is fully depleted.

10. The memory cell according to claim 1, which further comprises

a trench formed within the channel, wherein the gate dielectric layer is formed on the walls of the trench and the floating gate is formed in the trench on the gate dielectric layer, so as to be isolated from the channel.

11. The memory cell according to claim 10, which further comprises a source region and a drain region in the thin film layer that are arranged asymmetrically on either side of the floating gate formed in the trench, so that the drain region is closer to the floating gate than is the source region.

12. An array of memory cells having a structure according to claim 1, wherein a plurality of memory cells are arranged in rows and in columns, and in which a back gate line is coupled to the back control gate of each of the cells along a row or a column.

13. The array of memory cells according to claim 12, wherein a word line is coupled to the front control gate of each of the plurality of memory cells along a column, and in which the back gate line extends parallel to the word line.

14. The array of memory cells according to claim 12, wherein a first subset of the plurality of memory cells are FET memory cells having fully depleted channels, and a second subset of memory cells are DRAM memory cells with floating channels and control gates recessed in the channel.

15. The array of memory cells according to claim 12, which further comprises a source region and a drain region in the thin film layer wherein the source region is shared between two adjacent memory cells along either a row or a column within the array.

16. A method of controlling a flash memory cell according to claim 1, in which, during a cell programming operation, the front control gate and the back control gate are used in combination by applying a first positive voltage to the front control gate and a second positive voltage to the back control gate, such that the first voltage is less than the voltage needed to program the cell when no voltage is applied to the back control gate.

17. A method of fabricating a flash memory cell comprising:

forming an insulating layer on a base substrate;

forming a thin film layer of semiconductor material on the insulating layer to form a semiconductor-on-insulator substrate;

forming a channel in the thin film layer, wherein the channel forms part of a field effect transistor (FET);

forming a gate dielectric layer on the thin film layer above the channel;

forming a floating gate on the gate dielectric layer;

forming an inter-gate dielectric layer on the floating gate to thereby electrically isolate the floating gate;

forming a front control gate on the inter-gate dielectric layer above the floating gate and separated therefrom by the inter-gate dielectric; and

forming a back control gate within the base substrate directly under and adjacent the insulating layer, wherein the front and back control gates are designed to be used in combination to perform a cell programming operation.

18. A method of fabricating a memory array made of a plurality of FETs and DRAM cells, which comprises:

forming an insulating layer on a base substrate;

forming a thin film layer of semiconductor material on the insulating layer to form a semiconductor-on-insulator substrate;

forming a plurality of channels in the thin film layer, wherein each of the plurality of channels forms part of a memory cell in an array;

forming a trench in each of the plurality of channels created in the thin film layer;

forming a gate dielectric layer on the walls of each of the plurality of trenches;

forming a gate in each of the plurality of trenches on the gate dielectric layer by filling the trench with a gate material;

forming the inter-gate dielectric layer on a first subset of the plurality of the floating gates;

forming the front control gate on the inter-gate dielectric layer, for each of the cells of the first subset to thereby create a plurality of FET memory cells having floating gates; and

forming the front control gate directly on the gate material filling a second subset of trenches, different from the first subset, to create a plurality of DRAM memory cells having floating channels.