Methods of Forming CMOS Transistors with High Conductivity Gate Electrodes

• US 20110136313A1
• Filed: 11/09/2010
• Published: 06/09/2011
• Est. Priority Date: 12/08/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Chae Lyoung, Yoon, Boun, Lee, Jongwon, Han, Sang Yeob
• Granted Patent: US 8,252,675 B2
• Time in Patent Office: Days
• US Class Current: 438/299
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Provided is a method for manufacturing a MOS transistor. The method comprises providing a substrate having a first active region and a second active region; forming a dummy gate stack on the first active region and the second active region, the dummy gate stack comprising a gate dielectric layer and a dummy gate electrode; forming source/drain regions in the first active region and the second active region disposed at both sides of the dummy gate stack; forming a mold insulating layer on the source/drain region; removing the dummy gate electrode on the first active region to form a first trench on the mold insulating layer; forming a first metal pattern to form a second trench at a lower portion of the first trench, and removing the dummy gate electrode on the second active region to from a third trench on the mold insulating layer; and forming a second metal layer in the second trench and the third trench to form a first gate electrode on the first active region and a second gate electrode on the second active region.

Claims

1. A method of forming an insulated-gate transistor, comprising:

forming a gate insulating layer on a substrate;

forming a dummy gate electrode on the gate insulating layer;

forming electrically insulating spacers on sidewalls of the dummy gate electrode;

covering the spacers and the dummy gate electrode with an electrically insulating mold layer;

removing an upper portion of the mold layer to expose an upper surface of the dummy gate electrode;

removing the dummy gate electrode from between the spacers by selectively etching back the dummy gate electrode using the mold layer and the spacers as an etching mask;

depositing a first metal layer onto an upper surface of the mold layer and onto inner sidewalls of the spacers;

filling a space between the inner sidewalls of the spacers with a dummy filler layer that contacts the first metal layer;

removing an upper portion of the first metal layer from between the inner sidewalls of the spacers and the dummy filler layer;

removing the dummy filler layer from between the inner sidewalls of the spacers to expose the first metal layer; and

depositing a second metal layer onto a portion of the first metal layer extending between the inner sidewalls of the spacers to thereby define a metal gate electrode comprising a composite of the first and second metal layers.

2. The method of claim 1, wherein said filling a space is followed by a step of planarizing the dummy filler layer to expose a portion of the first metal layer on the upper surface of the mold layer.

3. The method of claim 1, wherein the dummy gate electrode and the dummy filler layer comprise the same materials.

4. The method of claim 1, wherein the dummy gate electrode and the dummy filler layer comprise polysilicon.

5. The method of claim 1, wherein said forming a dummy gate electrode on the gate insulating layer is preceded by forming a buffer gate electrode comprising titanium nitride or tantalum nitride on the gate insulating layer.

6. The method of claim 1, wherein said removing an upper portion of the first metal layer comprises selectively etching the first metal layer using the dummy filler layer and the mold layer as an etching mask.

7. The method of claim 5, wherein the first metal layer comprises titanium nitride.

8. A method of forming CMOS transistors, comprising:

forming first and second gate insulating layers on a substrate;

forming first and second dummy gate electrodes on the first and second gate insulating layers, respectively;

forming first and second electrically insulating spacers on sidewalls of the first and second dummy gate electrodes, respectively;

covering the first and second spacers and the first and second dummy gate electrodes with an electrically insulating mold layer;

removing an upper portion of the mold layer to expose an upper surface of the first dummy gate electrode and an upper surface of the second dummy gate electrode;

selectively removing the first dummy gate electrode from between the first spacers using a mask to prevent removal of the second dummy gate electrode;

depositing a first metal layer onto an upper surface of the mold layer and onto inner sidewalls of the first spacers;

filling a space between the inner sidewalls of the first spacers with a dummy filler layer that contacts the first metal layer;

removing an upper portion of the first metal layer from between the inner sidewalls of the first spacers and the dummy filler layer;

removing the dummy filler layer from between the inner sidewalls of the first spacers to expose the first metal layer concurrently with removing the second dummy gate electrode from between inner sidewalls of the second spacers; and

depositing a second metal layer onto a portion of the first metal layer extending between the inner sidewalls of the first spacers to thereby define a first metal gate electrode of comprising a composite of the first and second metal layers concurrently with depositing the second metal layer into a space between the inner sidewalls of the second spacers to thereby define a second metal gate electrode.

9. A method for manufacturing a MOS transistor, comprising:

providing a substrate having a first active region and a second active region;

forming a dummy gate stack on the first active region and the second active region, the dummy gate stack comprising a gate dielectric layer and a dummy gate electrode;

forming source/drain regions in the first active region and the second active region disposed at both sides of the dummy gate stack;

forming a mold insulating layer on the source/drain regions;

removing the dummy gate electrode on the first active region to form a first trench on the mold insulating layer;

forming a first metal pattern at a lower portion of the first trench to form a second trench, and removing the dummy gate electrode on the second active region to from a third trench in the mold insulating layer; and

forming a second metal layer in the second trench and the third trench to form a first gate electrode on the first active region and a second gate electrode on the second active region.

10. The method of claim 9, wherein the forming of the second trench and the third trench comprises:

stacking a first metal layer and a dummy filler layer on a top surface of the mold insulating layer and in the first trench;

planarizing the dummy filler layer to expose the first metal layer; and

removing the first metal layer on the top surface of the mold insulating layer and removing an upper portion of the first metal layer formed between the mold insulating layer and the dummy filler layer to form the first metal pattern at the lower portion of the first trench.

11. The method of claim 10, wherein the dummy gate electrode and the dummy filler layer are formed of the same material.

12. The method of claim 11, wherein the dummy gate electrode and the dummy filler layer are formed of polysilicon.

13. The method of claim 11, wherein the forming of the second trench and the third trench further comprises:

removing the filler layer on the first active region and the dummy gate electrode on the second active region to form the second trench on the first active region and the third trench on the second active region.

14. The method of claim 11, wherein the first metal layer is removed by an etching method in which the first metal layer is etched with etching selectivity to the dummy filler layer and the mold insulating layer.

15. The method of claim 11, wherein the first metal layer is removed while remaining at a bottom surface and a side lower portion of the first trench to form the first metal pattern.

16. The method of claim 10, further comprising:

forming a spacer on a sidewall of the dummy gate electrode.

17. The method of claim 10, further comprising:

forming a buffer gate electrode between the gate insulating layer and the dummy gate electrode.

18. The method of claim 17, wherein the buffer gate electrode comprises titanium nitride or tantalum nitride.

19. The method of claim 10, wherein the forming of the first gate electrode and the second gate electrode comprises:

forming the second metal layer on the entire surface of the substrate including the second trench and the third trench; and

planarizing the second metal layer down to a top surface of the mold layer to isolate the first gate electrode and the second gate electrode from each other.

20. The method of claim 10, wherein forming the second metal layer in the second trench and the third trench respectively.