Semiconductor Component and Method for Producing a Semiconductor Component

• US 20110147843A1
• Filed: 12/15/2010
• Published: 06/23/2011
• Est. Priority Date: 12/22/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Zundel, Markus, Wood, Andrew, Zelsacher, Rudolf
• Granted Patent: US 8,269,282 B2
• Time in Patent Office: Days
• US Class Current: 257/365
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor component includes at least one field effect transistor disposed along a trench in a semiconductor region and has at least one locally delimited dopant region in the semiconductor region. The at least one locally delimited dopant region extends from or over a pn junction between the source region and the body region of the transistor or between the drain region and the body region of the transistor into the body region as far as the gate electrode, such that a gap between the pn junction and the gate electrode in the body region is bridged by the locally delimited dopant region.

Claims

1. A semiconductor component, comprising:

at least one field effect transistor disposed along a trench in a semiconductor region, the at least one field effect transistor having a source region of a first conductivity type, a drain region of the first conductivity type, and a body region of a second conductivity type between the source region and the drain region in the semiconductor region;

a gate electrode in the trench along the body region, said gate electrode being arranged in a manner isolated from the body region by a gate dielectric;

at least one locally delimited dopant region of the first conductivity type in the semiconductor region, said at least one locally delimited dopant region extending from or over a pn junction between the source region and the body region or between the drain region and the body region, part of the dopant region lying in the body region opposite part of the gate electrode such that a gap in the body region between the pn junction and the gate electrode is bridged by the dopant region.

2. The semiconductor component according to claim 1, wherein the trench comprises a wide upper trench region and a narrower lower trench region such that a step is formed in the semiconductor region.

3. The semiconductor component according to claim 1, wherein the gate dielectric and the gate electrode are arranged in a first region of the trench and a field plate is arranged in a second region of the trench along the drain region, and the field plate is isolated from the drain region by a field plate dielectric.

4. The semiconductor component according to claim 3, wherein the gate electrode is isolated from the field plate by a dielectric.

5. A method for producing a semiconductor component, comprising:

forming a trench in a semiconductor region, the trench having an upper trench region and a lower trench region, the upper trench region being wider than the lower trench region such that a step is formed in the semiconductor region; and

introducing a dopant into the step to form a locally delimited dopant region in the semiconductor region.

6. The method according to claim 5, wherein the trench is firstly produced with a first width, in the lower trench region sidewalls of the semiconductor region are covered with a protective layer, and the upper trench region not covered by the protective layer is widened to a second width greater than the first width.

7. The method according to claim 6, wherein the non-covered sidewalls of the semiconductor region in the upper trench region are firstly converted into a sacrificial layer, and said sacrificial layer is subsequently removed selectively from the semiconductor region.

8. The method according to claim 5, wherein the trench is produced so that firstly only the upper trench region is produced with a first width, side walls of the upper trench region are covered with a protective layer and the lower trench region at a non-protected bottom of the upper trench region is subsequently produced further into the semiconductor region with a second width smaller than the first width.

9. The method according to claim 5, wherein the dopant is implanted into the semiconductor region.

10. The method according to claim 9, wherein the implantation is effected with an angle in the range of 0°

to 7°

with respect to a main surface normal of the semiconductor region.