SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20110147927A1
• Filed: 03/02/2011
• Published: 06/23/2011
• Est. Priority Date: 01/07/2009
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: HAGIHARA, Kiyomi
• Granted Patent: US 8,513,818 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/13005 Structure
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81011 Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81444 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/8191 Cleaning, e.g. oxide removal step, desmearing
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor device includes a semiconductor chip having an element formation surface on which at least one element is formed and including a plurality of electrode pads formed on the element formation surface, an interconnect substrate having a principal surface facing the element formation surface of the semiconductor chip and including a plurality of connection pads formed at positions of the principal surface facing the respective corresponding electrode pads, and a plurality of solder bumps provided between the respective corresponding electrode pads and connection pads, and configured to electrically connect the respective corresponding electrode pads and connection pads together. An UBM layer is formed on a portion of each solder bump closer to the corresponding electrode pad and a barrier metal layer is formed on a portion of each solder bump closer to the corresponding connection pad, and the two layers have substantially the same composition of major materials.

Claims

1. A semiconductor device comprising:

a semiconductor chip having an element formation surface on which at least one element is formed and including a plurality of electrode pads formed on the element formation surface;

an interconnect substrate having a principal surface facing the element formation surface of the semiconductor chip and including a plurality of connection pads formed at positions of the principal surface facing the respective corresponding electrode pads;

a first barrier layer formed on at least one of the plurality of electrod pads;

a second barrier layer formed on at least one of the plurality of connection pads; and

a plurality of solder bumps provided between the respective corresponding electrode pads and connection pads, and configured to electrically connect the respective corresponding electrode pads and connection pads together,

wherein

the first and second barrier layers have substantially the same composition of major materials.

2. The semiconductor device of claim 1, wherein

the first barrier layer is formed on the at least one of the plurality of electrode pads other than those which are provided on corner portions of the semiconductor chip.

3. The semiconductor device of claim 2, wherein

the second barrier layer is formed on the at least one of the plurality of connection pads other than those which face the electrode pads provided on the corner portions of the semiconductor chip.

4. The semiconductor device of claim 3, wherein

the first and second barrier layers are both amorphous.

5. The semiconductor device of claim 3, wherein

the first and second barrier layers are both crystalline.

6. The semiconductor device of claim 3, wherein

the first and second barrier layers are each made of a nickel compound formed by electroless plating.

7. The semiconductor device of claim 3, wherein

the first and second barrier layers are each made of a nickel compound formed by electroplating.

8. The semiconductor device of claim 3, wherein

the plurality of solder bumps have substantially the same volume.

9. A method for fabricating a semiconductor device, comprising the steps of:

(a) selectively forming a plurality of electrode pads on an element formation surface of a semiconductor chip on which at least one element is formed;

(b) after (a), forming a first barrier layer containing a metal as a major component on at least one of the plurality of electrode pads by electroless plating;

(c) forming, on a principal surface of an interconnect substrate, connection pads at positions facing the respective corresponding electrode pads of the semiconductor chip;

(d) after (c), forming a second barrier layer containing the metal as a major component on at least one of the plurality of connection pads facing the first barrier layer of the interconnect substrate by electroless plating; and

(e) mounting the semiconductor chip onto the principal surface of the interconnect substrate by positioning the semiconductor chip and the interconnect substrate so that the electrode pads of the semiconductor chip face the respective corresponding connection pads of the interconnect substrate with the respective corresponding solder bumps being interposed therebetween, and bonding the semiconductor chip and the interconnect substrate together using the solder bumps.

10. The method of claim 9, wherein

in step (b), the first barrier layer is formed on the at least one of the plurality of electrode pads other than those which are provided on corner portions of the semiconductor chip.

11. The method of claim 10, wherein

the metal contained in the first and second barrier layers contains nickel as a major component.

12. The method of claim 10, wherein

in step (d), the second barrier layer is formed on the at least one of the plurality of connection pads other than those which face the electrode pads provided on corner portions of the semiconductor chip.

13. The method of claim 10, wherein

the plurality of solder bumps have substantially the same volume.

14. The method of claim 10, further comprising the step of:

(f) after step (e), filling a gap between the semiconductor chip and the interconnect substrate with an insulating resin material, and curing the insulating resin material.