PARASITIC CAPACITANCE CANCELLATION IN CAPACITIVE MEASUREMENT APPLICATIONS

• US 20110148440A1
• Filed: 10/15/2009
• Published: 06/23/2011
• Est. Priority Date: 10/15/2008
• Status: Active Grant

• Current Assignee: Azoteq Holdings Limited
• Original Assignee: Azoteq Pty Ltd.
• Inventors: Van Der Merwe, Douw Gerbrandt, Swanepoel, Johann, Bruwer, Frederick Johannes
• Granted Patent: US 8,659,306 B2
• Time in Patent Office: Days
• US Class Current: 324/684
• CPC Class Codes: G01D 5/24 by varying capacitance
• CPC Class Codes: G01D 5/2417 by varying separation
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: G01R 27/2611 Measuring inductance
• CPC Class Codes: H03K 17/955 using a capacitive detector
• CPC Class Codes: H03K 2217/960725 Charge-transfer

Abstract

An integrated circuit for compensating for parasitic capacitance in a capacitive measuring apparatus wherein a capacitance measurement is done by repeatedly transferring charge from a capacitor to be measured to a reference capacitor.

Claims

1-19. -19. (canceled)

20. An integrated circuit comprising a capacitive measurement circuit for use in a capacitive measurement circuit that is connected to a sense plate structure, wherein the integrated circuit implements at least one of the following techniques:

(a) the use of a current ratio, derived through at least one current mirror structure, to scale a charge transferred from the sense plate structure to the capacitive measurement circuit in order to achieve practical on-chip implementation; and

(b) the subtraction of an adjustable amount of charge through the use of selectable practical on-chip structures, from a charge in the capacitive measurement circuit that reflects the charge transferred from the sense plate structure to the capacitive measurement circuit, in order to effectively reduce the measured capacitance of the sense plate structure.

21. The integrated circuit of claim 20 wherein a charge transfer method is implemented to measure the capacitance of the sense plate structure and wherein a charge in the capacitive measurement circuit is reduced during every cycle of a charge transfer measurement by a pre-determined amount.

22. The integrated circuit of claim 20 wherein a sense plate structure capacitance cancellation technique, by removing charge from the capacitive measurement circuit, and a sense plate structure charge transfer capacitive measurement technique, are implemented using means comprising current mirror ratios to scale the amounts of charge removed and transferred.

23. The integrated circuit of claim 22 wherein the current mirror ratios allow for the scaling of on-chip reference capacitors used for implementing the capacitance cancellation technique and the charge transfer capacitive measurement technique.

24. The integrated circuit of claim 20 wherein the technique of 20(a) is implemented.

25. The integrated circuit of claim 20 wherein the technique of 20(b) is implemented.

26. The integrated circuit of claim 24 wherein a charge transfer capacitive measurement technique is implemented without external reference capacitors.

27. The integrated circuit of claim 25 which includes at least one current mirror structure with a ratio to scale the on-chip elements involved in removing the charge from the capacitive measurement circuit to implement an effective reduction in measured capacitance of the sense plate structure.

28. The integrated circuit of claim 27 wherein the selection of a capacitor from multiple capacitors is used to determine the amount of charge that is removed from the capacitive measurement circuit to implement the effective reduction in measured capacitance of the sense plate structure.

29. The integrated circuit of claim 27 wherein the selection of a reference current from multiple reference currents is used to determine the amount of charge that is removed from the capacitive measurement circuit to implement the effective reduction in measured capacitance of the sense plate structure.

30. The integrated circuit of claim 24 wherein, during operation, at least one capacitor is automatically selected, from multiple capacitors in the capacitive measurement circuit in which the charge reflecting the charge transferred from the sense plate structure is accumulated, according to an algorithm that is designed to optimize the capacitive measurement system performance based on a specific parameter or metric.

31. The integrated circuit of claim 25 wherein, during operation, a capacitor is automatically selected, in the capacitive measurement circuit, that determines, before a charge transfer cycle, the amount of charge to be removed from the capacitive measurement circuit in order to implement an effective reduction in measured capacitance of the sense plate structure, and wherein the automatic selection is made according to an algorithm to optimize the performance of the capacitive measurement system according to a parameter or metric.

32. The integrated circuit of claim 20 which implements techniques 20(a) and 20(b), and in which, during operation, at least one capacitor is dynamically selected, in the capacitive measurement circuit that implements the charge transfer measurement of the sense plate structure and the capacitive cancellation technique, according to an algorithm to optimize the performance of the capacitive measurement system according to a parameter or metric.

33. The integrated circuit of claim 25 wherein at least one current source in the capacitive measurement circuit is automatically selected, to predetermine the amount of charge to be removed from the capacitive measurement circuit to implement an effective reduction in measured capacitance of the sense plate structure, in accordance with an algorithm that optimizes the performance of the capacitive measurement system according to a parameter or metric.

34. The integrated circuit of claim 20 which implements techniques 20(a) and 20(b), and which includes a noise detection circuit for detecting noise present in the silicon and wherein an output of the noise detection circuit is used to reduce the effect of such noise on the functionality of the integrated circuit.

35. The integrated circuit of claim 20 which implements techniques 20(a) and 20(b), and wherein the number of charge transfer cycles in a measurement cycle of the sense plate structure capacitance is modified by adjusting the amount of charge to be removed in technique 20(a) according to an algorithm.

36. The integrated circuit of claim 30 wherein the algorithm is chosen to optimize the performance of the capacitive measurement circuit for sensitivity.

37. The integrated circuit of claim 31 wherein the algorithm is chosen to optimize the performance of the capacitive measurement circuit for sensitivity.

38. A method of adjusting the number of charge transfer cycles in a capacitive measurement cycle of a capacitive measurement circuit which includes a sense plate structure, an integrated on-chip reference capacitor wherein a charge, reflecting the size of the capacitance of the sense plate structure, is accumulated and current mirror ratios structures, the method including the step of optimizing the capacitive measurement circuit performance in terms of a selected parameter, by dynamically adjusting at least one of the following parameters in accordance with an algorithm:

(a) a current mirror ratio;

(b) the size of the on-chip reference capacitor; and

(c) an amount of charge to be removed from the capacitive measurement circuit during each cycle of the charge transfer measurement, using selectable on-chip structures, in order to reduce the measured capacitance of the sense plate structure.

39. The method of claim 38 wherein at least two of said parameters are adjusted to optimize the performance of the capacitive measurement circuit for sensitivity.

40. The method of claim 38 which includes the steps of detecting noise by using a measurement circuit for noise that is not influenced by the capacitance of an object proximate or touching the sense plate structure and using information which is dependent on the detection of such noise to reduce the effect of the noise on the operation of the capacitive measurement circuit.