MULTILEVEL MEMORY BUS SYSTEM FOR SOLID-STATE MASS STORAGE

• US 20110161568A1
• Filed: 09/07/2010
• Published: 06/30/2011
• Est. Priority Date: 09/07/2009
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO Networks, Inc.
• Inventors: Baylon, Joel Alonzo, Villapana, Elsbeth Lauren Tagayo, Bruce, Ricardo H.
• Granted Patent: US 8,447,908 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/36 for access to common bus or bus system

Abstract

The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.

Claims

1. A multilevel memory bus system for a solid-state storage device that includes a plurality of semiconductor memory devices, a host interface, at least one flash-specific-DMA controller, and a local processing system that includes a local memory, the multilevel memory bus system comprising:

an intermediate bus disposed to couple to said at least one flash-specific DMA controller;

a first flash memory bus disposed to couple to at least one semiconductor memory device from the plurality of semiconductor memory devices, said at least one semiconductor memory device including a first semiconductor memory device;

a first flash buffer circuit coupled to said intermediate bus and to said first flash memory bus; and

wherein said intermediate bus is disposed to transfer data at a first data path transfer rate, said first memory bus transfer data is disposed to transfer data at a second data path transfer rate, and said first and second data path transfer rates are different.

2. The multilevel memory bus system of claim 1, further including:

a first output that provides a first data path clock signal having a first clock frequency;

a second output that provides a second data path clock signal having a second clock frequency; and

said first clock frequency is at least equal to said second clock frequency.

3. The multilevel memory bus system of claim 2, wherein:

said intermediate bus includes a first data path having a first bus width; and

said first flash buffer circuit includes a first intermediate bus interface having an interface data throughput that is proportional to said first bus width, said first clock frequency, and a selected sampling rate.

4. The multilevel memory bus system of claim 3, further including a strobe output disposed to provide a first strobe signal having a first strobe frequency.

5. The multilevel memory bus system of claim 4, wherein said selected sampling rate is equal to a selected integer multiple of said first strobe frequency.

6. The multilevel memory bus system of claim 4, wherein said selected sampling rate is at least twice that of said first strobe frequency.

7. The multilevel memory bus system of claim 4, wherein said first strobe frequency signal further includes a plurality of rising edges;

and said first flash buffer circuit samples data on said intermediate bus each time a rising edge from said plurality of rising edges is provided by said strobe output.

8. The multilevel memory bus system of claim 4, wherein said first strobe signal further includes a plurality of rising edges;

and said first flash buffer circuit samples data on said intermediate bus each time a rising edge from said plurality of rising edges is provided by said strobe output.

9. The multilevel memory bus system of claim 8, wherein said at least one flash-specific DMA controller includes a first flash-specific DMA controller, said first flash-specific DMA controller disposed to strobe said data on said intermediate bus at a frequency equal to said first strobe frequency only during a data transfer phase.

10. The multilevel memory bus system of claim 4, wherein said first strobe signal further includes a plurality of rising edges and a plurality of falling edges;

and said first flash buffer circuit samples data on said intermediate bus each time an edge from said plurality of rising edges or said plurality of falling edges is provided by said strobe output.

11. The multilevel memory bus system of claim 3, wherein one edge from said plurality of falling edges and another edge from said plurality of rising edges occur with the same period of said first strobe frequency.

12. The multilevel memory bus system of claim 6, wherein said intermediate bus interface has an interface data throughput that is defined by:

IBthru=DataWidth_IB*FREQfactor*FREQ*DS

where said IBthru is equal to said interface data throughput, said DataWidth_IB is equal to said first bus width, said FREQfactor is equal to the quotient of said first frequency divided by said second clock frequency rounded to the nearest integer, said FREQ is equal to said second clock frequency, and said DS is equal to said selected integer multiple.

13. The multilevel memory bus system of claim 12, wherein:

said first memory bus further includes first memory bus width;

said first flash buffer circuit further includes a first memory bus interface having a memory bus data throughput that is proportional to said first memory bus width and said second clock frequency.

14. The multilevel memory bus system of claim 13, wherein said interface data throughput is equivalent to said first data path transfer rate and said memory bus data throughput is equal to said second data path transfer rate.

15. The multilevel memory bus system of claim 6, wherein said flash memory bus interface has a flash memory bus interface data throughput that is defined by:

FMBUS=DataWidth_FMB*FREQ

where said IBthru is equal to said flash memory bus interface data throughput, said DataWidth_FMB is equal to said second bus width, and said FREQ is equal to said second clock frequency.

16. The multilevel memory bus system of claim 1, wherein said flash buffer circuit includes an internal buffer for buffering data received from said flash-specific DMA controller or from said semiconductor memory device.

17. The multilevel memory bus system of claim 1, further including dedicated busy lines.

18. The multilevel memory bus system of claim 1, further including:

a second flash buffer circuit coupled to said intermediate bus;

an exclusive busy circuit disposed to monitor time multiplexed signals from said first and second flash buffer circuits.

19. The multilevel memory bus system of claim 1, further including an exclusive busy circuit disposed to monitor a busy signal generated by said first semiconductor memory device.

20. The multilevel memory bus system of claim 1, further including an exclusive busy circuit disposed to monitor a busy signal generated by said first semiconductor memory device

21. A storage device, comprising:

a local processing system that includes a local memory, a local bus, at least one flash-specific DMA controller, including a first flash-specific DMA controller, and a host interface;

an intermediate bus coupled to said at least one flash-specific DMA controller;

a plurality of semiconductor memory devices, including a first semiconductor memory device;

a first flash memory bus coupled to said first semiconductor device;

a first flash buffer circuit coupled to said intermediate bus and to said first memory bus; and

an adaptability mechanism disposed to transfer data across said intermediate bus at a first data path transfer rate and across said first memory bus at a second data path transfer rate that is different from said first data path transfer rate.

22. The multilevel memory bus system of claim 21, wherein said intermediate bus interface and a memory bus interface are formed are part of said first flash buffer circuit.

23. The storage device of claim 21, wherein said adaptability mechanism includes an intermediate bus interface and a flash memory bus interface, said intermediate bus interface disposed to transfer data at an interface data throughput, said memory bus interface disposed to transfer data at a memory bus interface throughput, and said interface data throughput and said memory bus interface through are different.

24. The storage device of claim 23, wherein said interface data throughput is equivalent to said first data path transfer rate and said memory bus data throughput is equal to said second data path transfer rate.

25. The storage device of claim 21, wherein said flash buffer circuit includes an internal buffer for buffering data received from said flash-specific DMA controller or from said semiconductor memory device.

26. The storage device of claim 21, further including dedicated busy lines.

27. The storage device of claim 21, further including:

a second flash buffer circuit coupled to said intermediate bus;

an exclusive busy circuit disposed to monitor time multiplexed signals from said first and second flash buffer circuits.

28. The storage device of claim 21, further including an exclusive busy circuit disposed to monitor a busy signal generated by said first semiconductor memory device.

29. The storage device of claim 21, further including an exclusive busy circuit disposed to monitor a busy signal generated by said first semiconductor memory device

30. The storage device of claim 21, further including:

a first output that provides a first data path clock signal having a first clock frequency;

a second output that provides a second data path clock signal having a second clock frequency; and

said first clock frequency is at least equal to said second clock frequency.

31. The storage device of claim 21, wherein:

said intermediate bus includes a first data path having a first bus width; and

said first flash buffer circuit includes a first intermediate bus interface having an interface data throughput that is proportional to said first bus width, a first clock frequency, and a selected sampling rate.

32. The storage device of claim 31, further including a strobe output disposed to provide a first strobe signal having a first strobe frequency.

33. The storage device of claim 32, wherein said selected sampling rate is equal to a selected multiple of said first strobe frequency.

34. The storage device of claim 33, wherein said interface data throughput is defined by:

IBthru=DPWib*FREQfactor*FREQ*DS

where said IBthru is equal to said interface data throughput, said DPWib is equal to said first bus width, said FREQfactor is equal to the quotient of said first frequency divided by said second clock frequency rounded to the nearest integer;

said FREQ is equal to said second clock frequency, and said DS is equal to said selected integer multiple.

35. The storage device of claim 34, wherein:

said first memory bus further includes first memory bus width;

said first flash buffer circuit further includes a first memory bus interface having a memory bus data throughput that is proportional to said first memory bus width and said second clock frequency.

36. The storage device of claim 35, wherein said interface data throughput is equivalent to said first data path transfer rate and said memory bus data throughput is equal to said second data path transfer rate.