Methods and Apparatus for Parallelizing Heterogeneous Network Communication in Smart Devices

• US 20110161974A1
• Filed: 12/28/2009
• Published: 06/30/2011
• Est. Priority Date: 12/28/2009
• Status: Active Grant

• Current Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Original Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Inventors: Takano, Kosuke, Yoshida, Naofumi, Kurabayashi, Shuichi
• Granted Patent: US 9,229,779 B2
• Time in Patent Office: Days
• US Class Current: 718/104
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/5066 Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs mappping at compile time, see G06F8/451

Abstract

The present disclosure relates to devices, implementations and techniques for task scheduling. Specifically, task scheduling in an electronic device that has a multi-processing environment and support network interface devices.

Claims

1. A task scheduling device operatively coupled to a device having multiple processor cores and supporting multiple network interface devices, comprising:

a task analyzer unit configured to select an allocation strategy for a task, based at least in part on an attribution of the task; and

a task allocator unit configured to allocate the task to one or more processor cores, based at least in part on the selected allocation strategy.

2. A task scheduling device as recited in claim 1, wherein the task analyzer unit is configured to select the allocation strategy for the task, based at least in part on the attribution of the task regarding a network interface device.

3. A task scheduling device as recited in claim 1, wherein the task analyzer unit is configured to select the allocation strategy for the task, based at least in part on one of or any combination of the attributions of the task regarding latency, data size, CPU usage, and parallelism.

4. A task scheduling device as recited in claim 1, wherein the task analyzer unit is configured to retrieve the attribution of the task from a program file being operatively associated with the task.

5. A task scheduling device as recited in claim 1, wherein the task analyzer unit is configured to select the allocation strategy for the task, by referring to a table storing the attribution of the task and the associated allocation strategy.

6. A task scheduling device as recited in claim 1, wherein the task analyzer unit is configured to make a list of sub-tasks of the task.

7. A task scheduling device as recited in claim 1, wherein the allocation strategy includes allocating a single task to a single processor core.

8. A task scheduling device as recited in claim 1, wherein the allocation strategy includes allocating a single task to multiple processor cores.

9. A task scheduling device as recited in claim 1, wherein the allocation strategy includes allocating multiple tasks to a single processor core.

10. A task scheduling device as recited in claim 1, wherein the allocation strategy includes allocating multiple tasks to multiple processor cores.

11. A task scheduling device as recited in claim 1, further comprising a resource checker unit configured to monitor usage of each CPU and available bandwidth of each network interface.

12. A task scheduling device as recited in claim 11, wherein the task allocator unit is configured to allocate the task to one or more processor cores, based at least in part on the allocation strategy and data regarding usage of each CPU and available bandwidth of each network interface being received from the resource checker unit.

13. A task scheduling device as recited in claim 1, wherein the task allocator unit is further configured to prepare a thread or a process for executing the task on the one or more processor cores.

14. A task scheduling device as recited in claim 13, further comprising a scheduler unit configured to control execution of the thread and/or the process.

15. A task scheduling method used for a device having multiple processor cores and supporting multiple network interface devices, comprising:

selecting an allocation strategy for a task, based on an attribution of the task; and

allocating the task to one or more processor cores, based at least in part on the selected allocation strategy.

16. A task scheduling method as recited in claim 15, wherein selecting the allocation strategy for the task comprises selecting the allocation strategy for the task based at least in part on the attribution of the task regarding a network interface device.

17. A task scheduling method as recited in claim 15, wherein selecting the allocation strategy for the task comprises selecting the allocation strategy for the task based at least in part on one of or any combination of the attributions of the task regarding latency, data size, CPU usage, and parallelism.

18. A task scheduling method as recited in claim 15, wherein selecting the allocation strategy for a task, based on an attribution of the task comprises selecting the allocation strategy for a task by retrieving the attribution of the task from a program file being operatively associated with the task.

19. A task scheduling method as recited in claim 15, wherein selecting the allocation strategy for a task, based on an attribution of the task comprises selecting the allocation strategy for a task by referring to a table storing the attribution of the task and the associated allocation strategy.

20. An article comprising:

a signal bearing medium comprising machine-readable instructions stored thereon, which, if executed by one or more processors, operatively enable a computing device to;

select an allocation strategy for a task, based on an attribution of the task; and

allocate the task to one or more processor cores, based at least in part on the selected allocation strategy.