Body-Tied Asymmetric N-Type Field Effect Transistor

• US 20110163380A1
• Filed: 01/07/2010
• Published: 07/07/2011
• Est. Priority Date: 01/07/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Chang, Leland, Chang, Josephine B., Sleight, Jeffrey W., Lin, Chung-Hsun
• Granted Patent: US 8,643,107 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78615 with a body contact

Abstract

In one exemplary embodiment of the invention, an asymmetric N-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric N-type field effect transistor is operable to act as a symmetric N-type field effect transistor.

Claims

1. An asymmetric N-type field effect transistor comprising:

a source region coupled to a drain region via a channel;

a gate structure overlying at least a portion of the channel;

a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and

a body-tie coupled to the channel.

2. The asymmetric N-type field effect transistor as in claim 1, where the asymmetric N-type field effect transistor is operable to act as a symmetric N-type field effect transistor.

3. The asymmetric N-type field effect transistor as in claim 1, where the halo implant is partially disposed in the source region.

4. The asymmetric N-type field effect transistor as in claim 1, where the halo implant is formed by an angled implant procedure.

5. The asymmetric N-type field effect transistor as in claim 4, where the angled implant procedure uses the gate structure to mask at least a portion of the drain region.

6. The asymmetric N-type field effect transistor as in claim 1, where the body-tie comprises at least one of:

an H-gate, a T-gate, a Schottky structure and a body-source tie.

7. The asymmetric N-type field effect transistor as in claim 1, where the asymmetric N-type field effect transistor comprises an asymmetric silicon-on-insulator N-type field effect transistor.

8. A semiconductor device comprising a plurality of asymmetric N-type field effect transistors, where each one of the plurality of asymmetric N-type field effect transistors comprises a source region coupled to a drain region via a channel, a gate structure overlying at least a portion of the channel, a halo implant disposed at least partially in the channel, and a body-tie coupled to the channel, where the halo implant is disposed closer to the source region than the drain region.

9. The semiconductor device as in claim 8, where at least one of the plurality of asymmetric N-type field effect transistors is operable to act as a symmetric N-type field effect transistor.

10. The semiconductor device as in claim 8, where the semiconductor device does not comprise a symmetric field effect transistor.

11. The semiconductor device as in claim 8, where the halo implant is formed by an angled implant procedure that uses the gate structure to mask at least a portion of the drain region.

12. The semiconductor device as in claim 8, where the body-tie comprises at least one of:

an H-gate, a T-gate, a Schottky structure and a body-source tie.

13. The semiconductor device as in claim 8, where the plurality of asymmetric N-type field effect transistors comprises a plurality of asymmetric silicon-on-insulator N-type field effect transistors.

14. An asymmetric N-type field effect transistor comprising a source region, a drain region, a P-type channel, a halo implant disposed at least partially in the channel, a gate structure and a body-tie, where the halo implant is disposed closer to the source region than the drain region and the asymmetric N-type field effect transistor is operable to act as a symmetric N-type field effect transistor due to the body-tie and asymmetric halo implant.

15. The asymmetric N-type field effect transistor as in claim 14, where the halo implant is partially disposed in the source region.

16. The asymmetric N-type field effect transistor as in claim 14, where the body-tie comprises at least one of:

an H-gate, a T-gate, a Schottky structure and a body-source tie.

17. The asymmetric N-type field effect transistor as in claim 14, where the asymmetric N-type field effect transistor comprises an asymmetric silicon-on-insulator N-type field effect transistor.

18. The asymmetric N-type field effect transistor as in claim 14, further comprising a source extension implant and a drain extension implant.

19. The asymmetric N-type field effect transistor as in claim 14, where the angled halo implant comprises at least one of boron and indium.

20. A method for forming an asymmetric N-type field effect transistor comprising:

forming a source region and a drain region coupled thereto via a channel;

forming a gate structure overlying at least a portion of the channel;

performing an angled implant to form a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and

forming a body-tie coupled to the channel.

21. The method as in claim 20, where the asymmetric N-type field effect transistor is operable to act as a symmetric N-type field effect transistor.

22. The method as in claim 20, where the halo implant is partially disposed in the source region.

23. The method as in claim 20, where the body-tie comprises at least one of:

an H-gate, a T-gate, a Schottky structure and a body-source tie.

24. The method as in claim 20, where the source region, drain region and channel overly a buried oxide layer, where the buried oxide layer overlies a silicon substrate.

25. The method as in claim 20, where the asymmetric N-type field effect transistor comprises an asymmetric silicon-on-insulator N-type field effect transistor.