UNBOUNDED TRANSACTIONAL MEMORY SYSTEM AND METHOD

• US 20110167222A1
• Filed: 12/09/2010
• Published: 07/07/2011
• Est. Priority Date: 01/05/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd., Seoul National University R&DB Foundation (Seoul National University)
• Original Assignee: Samsung Electronics Co. Ltd., Seoul National University R&DB Foundation (Seoul National University)
• Inventors: LEE, Jaejin, Choi, Jong-Deok, Cho, Seung-Mo
• Granted Patent: US 8,706,973 B2
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/528 by using speculative mechanisms

Abstract

An unbounded transactional memory system which can process overflow data. The unbounded transactional memory system may include a host processor, a memory, and a memory processor. The host processor may include an execution unit to perform a transaction, and a cache to temporarily store data. The memory processor may store overflow data in overflow storage included in the memory in response to an overflow event in which the overflow data is generated in the cache during the transaction.

Claims

1. An unbounded transactional memory system, comprising:

a host processor comprising;

an execution unit configured to perform a transaction; and

a cache configured to temporarily store data;

a memory; and

a memory processor configured to store overflow data in overflow storage included in the memory in response to an overflow event in which the overflow data is generated in the cache during the transaction.

2. The unbounded transactional memory system of claim 1, wherein the cache comprises a plurality of cache sets, each cache set comprising a plurality of cache lines, each cache line comprising a T bit configured to indicate whether the cache line is accessed by a transaction, each cache set comprising an O bit configured to indicate whether the cache set has overflowed.

3. The unbounded transactional memory system of claim 2, wherein, in response to data generated by a transaction being greater than a size of a cache set to store the data, the host processor is configured to:

generate an overflow event;

set an O bit in the cache set; and

transmit the overflow event to the memory processor to inform of the occurrence of the overflow event.

4. The unbounded transactional memory system of claim 1, wherein the host processor further comprises a transaction counter register configured to indicate a number of nested transactions.

5. The unbounded transactional memory system of claim 1, wherein the host processor further comprises a register check point register configured to store data that has been previously generated during execution of previous instructions before a transaction_begin instruction, in response to the host processor executing the transaction_begin instruction.

6. The unbounded transactional memory system of claim 1, wherein:

in response to the transaction that causes the overflow event being committed, the host processor is configured to generate a commit_transaction event; and

the memory processor is further configured to flush the overflow data to the memory in response to the commit_transaction event.

7. The unbounded transactional memory system of claim 1, wherein:

in response to the transaction that causes the overflow event being aborted, the host processor is configured to generate an abort_transaction event; and

the memory processor is further configured to invalidate the overflow data from the overflow storage in response to the abort_transaction event.

8. The unbounded transactional memory system of claim 2, wherein:

in response to the host processor comprising the cache set with an O bit set therein performing the transaction that causes the overflow event and a different host processor requesting data from the memory in its own transaction, the host processor is configured to generate a conflict_detection event; and

the memory processor is further configured to determine whether an address of the requested data is stored in the overflow storage, in response to the conflict_detection event.

9. The unbounded transactional memory system of claim 2, wherein:

in response to a cache miss occurring in the host processor comprising the cache set with an O bit set therein while the transaction that causes the overflow event is performed, the host processor is configured to generate a cache_miss event; and

the memory processor is further configured to determine whether data of an address at which the cache miss occurs is stored in the overflow storage, in response to the cache_miss event.

10. The unbounded transactional memory system of claim 1, wherein the memory processor comprises:

a handler configured to process an event received from the host processor; and

a plurality of registers configured to be set for processing the event, the plurality of registers comprising;

a processor identification register;

a data register;

an address register;

a cache state register; and

an event notification register.

11. The unbounded transactional memory system of claim 1, wherein the overflow storage comprises a hash table corresponding to the host processor, the hash table configured to store the overflow data in a storage space indexed by a value hashed from an address of the overflow data.

12. The unbounded transactional memory system of claim 1, wherein, in response to a plurality of host processors being present, the overflow storage comprises a global hash table configured to store overflow data of the respective host processors using processor IDs of the respective host processors.

13. A method of operating a unbounded transactional memory system comprising a host processor comprising an execution unit to perform a transaction and a cache to temporarily store data, a memory, and a memory processor interposed between the host processor and the memory, the method comprising:

is generating an overflow event in response to data being overflowed in the cache of the host processor that is performing the transaction; and

in response to the overflow event, storing the overflow data in overflow storage included in the memory using the memory processor.

14. The method of claim 13, wherein the cache comprises a plurality of cache sets, each cache set comprising a plurality of cache lines, each cache line comprising a T bit indicating whether the cache line is accessed by a transaction, each cache set comprising an O bit indicating whether the cache set has been overflowed.

15. The method of claim 14, wherein the generating of the overflow event comprises:

in response to data generated by a transaction being greater than a size of a cache set to store the data;

generating the overflow event; and

setting an O bit in the cache set; and

transmitting the overflow event to the memory processor to inform of the occurrence of the overflow event.

16. The method of claim 13, further comprising:

in response to the host processor executing the transaction_begin instruction, storing data that has been previously generated during execution of previous instructions before a transaction_begin instruction in a register check point register included in the host processor.

17. The method of claim 13, further comprising:

generating, at the host processor, a commit_transaction event in response to the transaction that causes the overflow event being committed; and

flushing, at the memory processor, the overflow data to the memory in response to the commit_transaction event.

18. The method of claim 13, further comprising:

generating, at the host processor, an abort_transaction event in response to the transaction that causes the overflow event being aborted; and

invalidating, at the memory processor, the overflow data from the overflow storage in response to the abort_transaction event.

19. The method of claim 14, further comprising:

in response to the host processor comprising the cache set with an O bit set therein performing the transaction that causes the overflow event and a different host processor requesting data from the memory in its own transaction, generating a conflict_detection event at the host processor;

determining, at the memory processor, whether an address of the requested data is stored in the overflow storage, in response to the conflict_detection event; and

transmitting the determination result from the memory processor to the host processor.

20. The method of claim 14, further comprising:

in response to a cache miss occurring in the host processor comprising the cache set with an O bit set therein while the transaction that causes the overflow event is performed, generating a cache_miss event at the host processor;

determining, at the memory processor, whether data of an address at which the cache miss occurs is stored in the overflow storage, in response to the cache_miss event; and

transmitting the determination result from the memory processor to the host processor.