MEMORY CELL WITH A CHANNEL BURIED BENEATH A DIELECTRIC LAYER

• US 20110169087A1
• Filed: 12/21/2010
• Published: 07/14/2011
• Est. Priority Date: 01/14/2010
• Status: Active Grant

• Current Assignee: Soitec S.A.
• Original Assignee: Soitec S.A.
• Inventors: MAZURE, CARLOS, FERRANT, RICHARD
• Granted Patent: US 8,304,833 B2
• Time in Patent Office: Days
• US Class Current: 257/348
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0711 in combination with bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7302 structurally associated with other devices assemblies of devices H01L25/00; integrated circuits H01L27/00; IGBT H01L29/7393
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

The invention provides various embodiments of a memory cell formed on a semiconductor-on-insulator (SeOI) substrate and comprising one or more FET transistors. Each FET transistor has a source region and a drain region at least portions of which are arranged in the thin layer of the SeOI substrate, a channel region in which a trench is made, and a gate region formed in the trench. Specifically, the source, drain and channel regions also have portions which are arranged also beneath the insulating layer of the SeOI substrate; the portion of channel region beneath the insulating layer extends between the portions of the source and drain regions also beneath the insulating layer; and the trench in the channel region extends into the depth of the base substrate beyond the insulating layer. Also, methods for fabricating such memory cells and memory arrays including a plurality of such memory cells.

Claims

1. A memory cell comprising:

a semiconductor-on-insulator (SeOI) substrate including a thin layer of semiconductor material separated from a base substrate by an insulating layer; and

an FET transistor including a source region and a drain region that are arranged at least essentially in the thin layer of the SeOI substrate, a channel in which a trench is made, and a gate region in the trench,

wherein the trench extends into the depth of the base substrate beyond the insulating layer, and

wherein the channel extends between the source region and the drain region at least essentially beneath the insulating layer.

2. The memory cell of claim 1 wherein the volume of the channel below the insulating layer is 200 to 1000 times the volume of the channel above the insulating layer.

3. The memory cell of claim 1, wherein the drain region and the source region are arranged integrally in the thin layer of the SeOI substrate, and wherein a channel conduction region is arranged at the insulating layer level on either side of the trench so that the channel extends between the source region and the drain region both above and beneath the insulating layer via the channel conduction region.

4. The memory cell of claim 3, wherein the FET transistor is partially depleted, and further comprising lateral isolation regions for isolating that part of the channel located above the insulating layer.

5. The memory cell of claim 1, wherein the source and drain regions extend both above and beneath the insulating layer via a source conduction zone and a drain conduction zone, respectively, the zones being arranged at the insulating layer level on either side of the trench, and wherein the channel extends integrally beneath the insulating layer between the parts of the source and drain regions that are located beneath the insulating layer.

6. The memory cell of claim 1, wherein the gate region is separated from the channel by a dielectric layer.

7. The memory cell of claim 1, wherein that part of the channel beneath the insulating layer is formed by a well made in the upper part of the base substrate.

8. The memory cell of claim 7, wherein the well is isolated from the remaining part of the base substrate by a layer of opposite conductivity to that of the well.

9. The memory cell of claim 1, further comprising lateral isolation regions which extend depthwise beneath the insulating layer for isolating that part of the channel located beneath the insulating layer.

10. The memory cell of claim 1, wherein the channel is floating, and wherein the gate region serves as control gate electrode for driving the FET transistor.

11. The memory cell of claim 10, further comprising a bipolar transistor having a collector that serves as the channel for the FET transistor.

12. The memory cell of claim 11, wherein the source of the FET transistor serves as the base for the bipolar transistor.

13. The memory cell of claim 11, wherein the base substrate serves as the base for the bipolar transistor.

14. The memory cell of claim 1, wherein the gate region is floating, and wherein the FET transistor further comprises a control gate electrode isolated from the floating gate region via a dielectric layer.

15. A memory array comprising a plurality of memory cells of claim 1.

16. A memory array comprising a plurality of memory cells of claim 11.

17. In a process for fabricating a memory cell in a semiconductor-on-insulator (SeOI) substrate comprising an FET transistor, the SeOI substrate including a thin layer of semiconductor material separated from a base substrate by an insulating layer, the FET transistor including a source region and a drain region that are arranged at least integrally in the thin layer of the SeOI substrate, and a channel region that extends between the source region and the drain region at least essentially beneath the insulating layer, the improvement which comprises:

forming a trench in the channel region that extends beyond the insulating layer;

providing the walls of the trench with a layer of a semiconductor material;

carrying out a recrystallization annealing operation on the semiconductor material on the walls of the trench so as to recrystallize the material in a single-crystalline state in the regions located above and beneath the insulating layer, and in a polycrystalline state at the insulating layer level, so as to define channel conduction regions on either side of the trench at the insulating layer level and the lateral faces of the trench;

providing the layer of semiconductor material on the walls of the trench with a dielectric layer; and

forming a gate region in the trench by filling the trench.

18. The improvement according to claim 17, wherein the semiconductor material and the dielectric layer completely cover the walls of the trench.

19. In a process for fabricating a memory cell in a semiconductor-on-insulator (SeOI) substrate comprising an FET transistor, the SeOI substrate including a thin layer of semiconductor material separated from a base substrate by an insulating layer, the FET transistor including a source region and a drain region arranged at least essentially in the thin layer of the SeOI substrate above the insulating layer, and a channel that extends integrally beneath the insulating layer, an improvement comprising:

forming, immediately beneath the insulating layer, a doped layer intended to define a further portion of the source region and a further portion of drain region that extend beneath the insulating layer on either side of a trench;

forming the trench in the semiconductor-on-insulator substrate so that the trench extends beyond the insulating layer between the parts of the source and drain regions that are located beneath the insulating layer;

providing the walls of the trench with a layer of semiconductor material;

providing the layer of semiconductor material on the walls of the trench with a dielectric layer;

forming a gate region by filling the trench; and

causing dopant to diffuse along the walls of the trench at the insulating layer level from the source and drain regions located above and beneath the insulating layer respectively, so as to form a source conduction zone and a drain conduction zone enabling the source regions and the drain regions, which extend above and beneath the insulating layer, respectively, to be connected.

20. The improvement according to claim 19, wherein the semiconductor material and the dielectric layer completely cover the walls of the trench.

21. In a process for fabricating a memory cell in a semiconductor-on-insulator (SeOI) substrate comprising an FET transistor, the SeOI substrate including a thin layer of semiconductor material separated from a base substrate by an insulating layer, the FET transistor including a source region and a drain region arranged at least essentially in the thin layer of the SeOI substrate above the insulating layer, and a channel that extends integrally beneath the insulating layer, an improvement comprising:

forming a first trench in the semiconductor-on-insulator substrate, the first trench extending from the surface of the semiconductor-on-insulator substrate down to the base substrate;

providing the walls of the first trench with spacers of a doped semiconductor material having a conductivity of the same type as those of the drain and source regions that extend above the insulating layer;

forming a second trench in the first trench, said second trench extending into the depth of the base substrate beyond the insulating layer from the bottom of the first trench;

providing the doped semiconductor material on the walls of said second trench and of the first trench with a dielectric layer;

forming a gate region by filling said second trench and the first trench; and

forming localized source and drain regions immediately beneath the insulating layer on either side of said second trench by dopant diffusion from the spacers, the spacers serving, after dopant diffusion, as channel conduction zones and drain conduction zones respectively, in order to connect the source and drain regions that extend above and beneath the insulating layer.

22. The improvement according to claim 21, wherein the doped semiconductor material and the dielectric layer completely cover the walls of the trench.