DEVICE HAVING A CONTACT BETWEEN SEMICONDUCTOR REGIONS THROUGH A BURIED INSULATING LAYER, AND PROCESS FOR FABRICATING SAID DEVICE

• US 20110169090A1
• Filed: 01/04/2011
• Published: 07/14/2011
• Est. Priority Date: 01/14/2010
• Status: Active Grant

• Current Assignee: Soitec S.A.
• Original Assignee: Soitec S.A.
• Inventors: Mazure, Carlos, Ferrant, Richard
• Granted Patent: US 9,490,264 B2
• Time in Patent Office: Days
• US Class Current: 257/350
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78639 with a drain or source connected to a bulk conducting substrate
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

The invention relates to a semiconductor device produced on a semiconductor-on-insulator substrate that includes a thin layer of semiconductor material separated from a base substrate by a buried insulating layer, the device including a first conducting region in the thin layer, a second conducting region in the base substrate and a contact connecting the first region to the second region through the insulating layer. The invention also relates to a process for fabricating such semiconductor devices.

Claims

1. A semiconductor device provided on a semiconductor-on-insulator substrate, wherein the substrate comprises a thin layer of semiconductor material separated from a base substrate by a buried insulating layer, and the device comprises a first conducting region in the thin layer, a second conducting region in the base substrate, and a contact connecting the first region to the second region through the insulating layer.

2. The device according to claim 1, wherein the first region is a drain region or a source region of a transistor and the second region belongs to a buried bit line or a buried source line.

3. The device according to claim 1, further comprising a source region and a channel region of a field effect transistor in the thin layer, wherein the first region constitutes the emitter of a bipolar transistor, the base of the bipolar transistor is formed by the source region and the collector of the bipolar transistor is formed by the channel region, and wherein the second region belongs to a buried injection line.

4. The device according to claim 1, wherein the second region is a back control gate region of a transistor and the first region belongs to a back control gate drive line.

5. The device according to claim 1, wherein the contact is formed from a doped semiconductor interconnect material.

6. The device according to claim 1, wherein the contact has a lower region the conductivity of which is the same as that of the first region, and an upper region of opposite conductivity.

7. The device according to claim 1, wherein the boundary between the upper region and the lower region is located in alignment with the insulating layer.

8. The device according to claim 1, wherein the boundary between the upper region and the lower region is located in alignment with the thin layer above the first region.

9. A process for fabricating a semiconductor device on a semiconductor-on-insulator substrate, wherein the substrate comprises a thin layer of semiconductor material separated from a base substrate by a buried insulating layer, and the device comprises a first conducting region in the thin layer, a second conducting region in the base substrate, wherein the process comprises providing a contact connecting the first region to the second region through the insulating layer.

10. The process according to claim 9, wherein the contact is formed by:

etching the semiconductor substrate in order to form therein a trench extending beyond the buried insulating layer, through the first region, and reaching the second region; and

filling of the trench with an interconnect material.

11. The process according to claim 10, wherein the interconnect material is a predoped semiconductor material.

12. The process according to claim 10, wherein the interconnect material is a semiconductor material and which further includes a step of doping the semiconductor material in the trench.

13. The process according to claim 12, wherein the doping of the semiconductor material in the trench is performed by an annealing operation that diffuse dopants in the trench.

14. The process according to claim 12, wherein upper and lower regions of the trench are oppositely doped.

15. The process according to claim 14, wherein the upper and lower regions have a boundary located in alignment with the insulating layer.

16. The process according to claim 14, wherein the upper and lower regions have a boundary located in alignment with the thin layer above the first region.