THROUGH-SILICON VIA FORMED WITH A POST PASSIVATION INTERCONNECT STRUCTURE

• US 20110169168A1
• Filed: 03/21/2011
• Published: 07/14/2011
• Est. Priority Date: 02/24/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: TSENG, Ming-Hong, JAO, Sheng Huang
• Granted Patent: US 8,390,125 B2
• Time in Patent Office: Days
• US Class Current: 257/771
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05082 Two-layer arrangements
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01041 Niobium [Nb]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

An integrated circuit structure includes a semiconductor substrate, a through-silicon via (TSV) extending into the semiconductor substrate, a pad formed over the semiconductor substrate and spaced apart from the TSV, and an interconnect structure formed over the semiconductor substrate and electrically connecting the TSV and the pad. The interconnect structure includes an upper portion formed on the pad and a lower portion adjacent to the pad, and the upper portion extends to electrically connect the TSV.

Claims

1. An integrated circuit structure, comprising:

a semiconductor substrate;

a through-silicon via (TSV) extending into the semiconductor substrate;

a pad formed over the semiconductor substrate and spaced apart from the TSV; and

an interconnect structure formed over the semiconductor substrate and electrically connecting the TSV and the pad;

wherein the interconnect structure comprises

an upper portion which is formed on the pad and extends to electrically connect the TSV; and

a lower portion outside the TSV and adjacent to the pad.

3. The integrated circuit structure of claim 1, wherein the interconnect structure and the TSV are formed of the same conductive material.

4. The integrated circuit structure of claim 1, wherein at least one of the TSV or the interconnect structure comprises copper.

5. The integrated circuit structure of claim 1, wherein the lower portion of the interconnect structure is positioned between the TSV and the pad.

6. The integrated circuit structure of claim 1, wherein the pad comprises aluminum or an aluminum alloy.

7. The integrated circuit structure of claim 1, further comprising

a passivation layer formed between the semiconductor substrate and the upper portion of the interconnect structure and surrounding the lower portion of the interconnect structure.

8. The integrated circuit structure of claim 7, wherein the passivation layer extends into the semiconductor substrate to line the sidewall and bottom of the TSV.

9. The integrated circuit structure of claim 7, wherein the passivation layer comprises two isolation layers.

10. The integrated circuit structure of claim 7, wherein the passivation layer comprises silicon oxide, silicon nitride, or a combination thereof.

15. The integrated circuit structure of claim 1, wherein the lower portion of the interconnect structure is co-elevational with the pad.

2. An integrated circuit structure, comprising:

a semiconductor substrate;

a through-silicon via (TSV) extending into the semiconductor substrate;

a pad formed over the semiconductor substrate and spaced apart from the TSV; and

an interconnect structure formed over the semiconductor substrate and electrically connecting the TSV and the pad;

wherein the interconnect structure comprises an upper portion formed on the pad and a lower portion adjacent to the pad, and the upper portion extends to electrically connect the TSV; and

wherein the lower portion of the interconnect structure is a ring surrounding the pad.

11. An integrated circuit structure, comprising:

a semiconductor substrate;

a low-k dielectric layer over the semiconductor substrate;

a metal line formed in the low-k dielectric layer;

a first passivation layer formed on the low-k dielectric layer and exposing a portion of the metal line;

a pad formed in the first passivation layer and on the exposed portion of the metal line;

a through-silicon via (TSV) passing through the first passivation layer and the low-k dielectric layer and extending into the semiconductor substrate, wherein the TSV is spaced apart from the pad; and

an interconnect structure formed over the first passivation layer and electrically connecting the TSV and the pad;

wherein the interconnect structure comprises

an upper portion which is formed directly on the pad and extends laterally into direct electrical connection with the TSV; and

a lower portion which extends from the upper portion toward the substrate, is located outside the TSV, and is free of direct contact with the TSV.

12. The integrated circuit structure of claim 11, wherein the lower portion of the interconnect structure is a ring surrounding the pad.

13. The integrated circuit structure of claim 11, wherein the interconnect structure and the TSV are formed of the same conductive material.

14. The integrated circuit structure of claim 11, wherein at least one of the TSV or the interconnect structure comprises copper.

16. The integrated circuit structure of claim 11, wherein the pad comprises at least one of aluminum, copper, an aluminum alloy, or a copper alloy.

17. The integrated circuit structure of claim 11, further comprising

a second passivation layer formed between the first passivation layer and the upper portion of the interconnect structure and surrounding the lower portion of the interconnect structure.

18. The integrated circuit structure of claim 17, wherein the second passivation layer extends into the semiconductor substrate to line the sidewall and bottom of the TSV.

19. The integrated circuit structure of claim 17, wherein the second passivation layer comprises at least one of silicon oxide, silicon nitride, or a combination thereof.

20. The integrated circuit structure of claim 11, wherein the first passivation layer comprises at least one of silicon oxide, silicon nitride, or a combination thereof.