INTERRELATED WiFi AND USB PROTOCOLS AND OTHER APPLICATION FRAMEWORK PROCESSES, CIRCUITS AND SYSTEMS

• US 20110188391A1
• Filed: 01/27/2011
• Published: 08/04/2011
• Est. Priority Date: 02/04/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sella, Assaf, Sherlock, Ian, Estevez, Leonardo W.
• Granted Patent: US 8,493,992 B2
• Time in Patent Office: Days
• US Class Current: 370/252
• CPC Class Codes: H04L 67/1051 Group master selection mechanisms
• CPC Class Codes: H04W 24/10 Scheduling measurement reports ; Arrangements for measurement reports
• CPC Class Codes: H04W 74/085 collision avoidance
• CPC Class Codes: H04W 88/08 Access point devices
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A master electronic circuit (300) includes a storage (324) representing a wireless collision avoidance networking process (332) involving collision avoidance overhead and combined with a schedulable process (345) including a serial data transfer process and a scheduler, a wireless modem (350) operable to transmit and receive wireless signals for the networking process (332), and a processor (320) coupled with the storage (324) and with the wireless modem (350) and operable to execute the scheduler to establish and transmit a schedule (110) for plural serial data transfers involving the processor (320) and distinct station identifications, and to execute the serial data transfers inside the wireless networking process and according to the schedule so as to avoid at least some of the collision avoidance overhead. Other electronic circuits, processes of making and using, and systems are disclosed.

Claims

1. A master electronic circuit comprising:

a storage representing a wireless collision avoidance networking process involving collision avoidance overhead and combined with a schedulable process including a serial data transfer process and a scheduler;

a wireless modem operable to transmit and receive wireless signals for the networking process; and

a processor coupled with said storage and with said wireless modem and operable to execute the scheduler to establish and transmit a schedule for plural serial data transfers involving the processor and distinct station identifications, and to execute the serial data transfers inside the wireless networking process and according to the schedule so as to avoid at least some of the collision avoidance overhead.

2. The master electronic circuit claimed in claim 1 wherein said processor is further operable according to the networking process to determine an available wireless medium data rate and to receive service requests via said wireless modem and to use both the wireless data rate and the service requests as input to the scheduler.

3. The master electronic circuit claimed in claim 1 wherein said processor is further operable according to the networking process to transmit the schedule by transmitting periodic beacon signals with the schedule entirely in a given beacon signal outside an interval between the periodic beacon signals.

4. The master electronic circuit claimed in claim 3 wherein said processor is further operable to generate the schedule for the given beacon signal based on A) an available wireless data rate for the serial data transfers, B) at least one latency datum, and C) at least one effective serial data rate datum.

5. The master electronic circuit claimed in claim 3 wherein said processor is further operable to generate the schedule for the given beacon signal to specify one or more station identifiers and for each specified station identifier to specify a type of data transfer, a start time for the data transfer, and a duration for the data transfer.

6. The master electronic circuit claimed in claim 1 wherein said processor is further operable to generate a second schedule having a duration datum representing at least one duration encompassing a pair of transfers in the first-named schedule.

7. The master electronic circuit claimed in claim 6 wherein said processor is further operable in accordance with the second schedule to generate medium protection control signals and use said wireless modem to transmit the medium protection control signals to protect the medium for the serial data transfers during an actual duration represented by the duration datum.

8. The master electronic circuit claimed in claim 1 wherein said processor is operable to conduct polling operations via said wireless modem and to execute the scheduler to schedule times for the serial data transfers responsive to a polling-received latency request for at least one of the serial data transfers.

9. The master electronic circuit claimed in claim 1 wherein said processor is operable to conduct polling operations via said wireless modem and to execute the scheduler to allocate time sub-intervals related in width to a polling-received requested data transfer bandwidth for at least one of the serial data transfers.

10. The master electronic circuit claimed in claim 1 wherein said processor is further operable to generate the schedule in a manner that effectively leaves a spacing interval between a pair of the scheduled serial data transfers and so that the spacing interval is wide enough for wireless collision avoidance networking operation.

11. A master electronic circuit comprising:

a storage representing a wireless networking program compatible with WiFi and combined with a data transfer process compatible with USB;

a wireless modem operable and compatible with WiFi; and

a processor coupled with said storage and with said wireless modem and operable to execute the wireless networking program to establish the circuit as a WiFi access point (AP) and thereby also as a USB wireless host for WiFi.

12. The master electronic circuit claimed in claim 11 wherein said processor is responsive to said wireless networking process to send WiFi beacons and to introduce a current schedule specifying a USB-compatible data transfer process into a said beacon only.

13. The master electronic circuit claimed in claim 12 wherein said processor is operable to designate one or more particular WiFi station identifications for the schedule.

14. The master electronic circuit claimed in claim 13 wherein the schedule includes a schedule of times in a next time interval between beacons for USB-like operations pertaining to those particular WiFi station identifications.

15. The master electronic circuit claimed in claim 12 wherein said processor is operable to conduct polling operations via said wireless modem and to respond to the polling operations to schedule the times so as to be related in their time position in the time interval between beacons to polling-requested maximum latency for USB-like operations.

16. The master electronic circuit claimed in claim 12 wherein said processor is operable to conduct polling operations via said wireless modem and to respond to the polling operations to allocate time sub-intervals related in width jointly to polling-requested data transfer bandwidth for USB-like operations and available wireless data transfer bandwidth.

17. The master electronic circuit claimed in claim 12 wherein said processor is operable to schedule at least one time sub-interval between beacons to be longer for USB-like operations if other WiFi non-USB-like operations become inactive.

18. The master electronic circuit claimed in claim 12 wherein said processor is operable to generate medium protection controls between beacons through said wireless modem and at least piecewise encompassing the schedule in a beacon, whereby enabling coexistence of a WiFi-based USB with the wireless networking.

19. The master electronic circuit claimed in claim 11 wherein said processor is operable as AP with said modem under control of USB host to establish a protected medium duration for USB-like wireless operations by a process selected from the group consisting of:

1) hybrid coordination function controlled channel access (HCCA),

     2) clear to send (CTS) to itself,

     3) notice of absence (NoA),

     4) separate channels.

20. The master electronic circuit claimed in claim 19 wherein said processor is operable to conduct a polling operation wirelessly inside a protected medium duration between beacons, and to subsequently schedule at least one time and duration parameter into a beacon but pertaining to the next interval between beacons and specifying one or more USB-like transfers in that next beacon-to-beacon interval.

21. The master electronic circuit claimed in claim 11 wherein said processor is operable in accordance with the wireless networking program to determine available wireless medium bandwidth, and said storage further has a scheduler module responsive to A) one or more service requests via said wireless modem, and B) the available wireless medium bandwidth to establish a schedule for USB-like operations.

22. The master electronic circuit claimed in claim 21 wherein said processor operating by the wireless networking module is responsive to said scheduler module to A) introduce into a beacon an information element having a schedule for between-beacons USB-like operations, and B) perform a wireless networking procedure to protect the wireless medium for the USB-like operations during time durations encompassing the schedule thus introduced.

23. The master electronic circuit claimed in claim 11 wherein the WiFi in said storage represents a peer-to-peer wireless networking process compatible with WiFi Direct combined with the data transfer process compatible with USB, and said processor is operable to execute the peer-to-peer wireless networking process to establish the processor as a WiFi Direct peer designated Group Owner and thereby also as USB-like wireless host inside WiFi Direct.

24. An electronic circuit comprising:

a storage representing a peer-to-peer wireless networking process compatible with WiFi Direct and combined with a data transfer process compatible with USB;

a wireless modem compatible with the WiFi Direct; and

a processor coupled with said storage and with said wireless modem and operable to execute a role negotiation via said wireless modem to selectively establish the circuit either as a WiFi Direct peer designated as a group owner or a WiFi Direct peer designated as a client device depending on a result of the role negotiation, said processor responsive to the result of group owner to operate as a USB host for the USB-like data transfer process wirelessly and said processor responsive to the result of client device to operate instead as a USB slave for the data transfer process wirelessly.

25. The electronic circuit claimed in claim 24 wherein WiFi Direct involves beacons and said processor is responsive as a USB-like slave to said wireless networking process to detect the beacons and further to detect a scheduling command for the USB-compatible data transfer process during each said beacon.

26. The electronic circuit claimed in claim 24 wherein WiFi Direct involves beacons and said processor as a USB-like host is operable to conduct a polling operation wirelessly inside a protected medium duration in the beacon-to-beacon interval, and to subsequently insert a schedule having at least one time and duration parameter for USB-like operations into a next beacon frame and prior to any protected medium duration in the next beacon-to-beacon interval, said processor operable to derive and produce each protected medium duration in that next beacon-to-beacon interval based on the schedule.

27. A slave electronic circuit comprising:

a storage representing a wireless collision avoidance networking process involving collision avoidance overhead and combined with a schedule-driven serial data transfer process;

a wireless modem operable to transmit and receive wireless signals for the networking process; and

a processor coupled with said storage and with said wireless modem and operable to receive a schedule for plural serial data transfers involving the processor and distinct station identifications, and to execute any serial data transfers scheduled for the slave inside the wireless networking process and according to the schedule so as to avoid at least some of the collision avoidance overhead.

28. The slave electronic circuit claimed in claim 27 wherein the wireless collision avoidance networking process involves detection of periodic beacon signals and said processor is further operable according to the networking process to obtain the schedule entirely from a given beacon signal independent of an interval between the periodic beacon signals.

29. The slave electronic circuit claimed in claim 27 wherein the processor coupled with said storage is operable to generate a service request and transmit the service request via said wireless modem.

30. The slave electronic circuit claimed in claim 27 wherein the schedule has at least one station identifier and for each specified station identifier the schedule specifies a type of data transfer and scheduled time for that data transfer, and said processor is further operable to respond to a portion of the schedule that specifies a station identifier identifying the slave itself.

31. The slave electronic circuit claimed in claim 30 wherein said processor is further operable to receive a medium protection control signal via said wireless modem and to responsively prevent transmission via said wireless modem unless the specified station identifier has identified the slave itself for serial data transfer transmission from the slave at a scheduled time under medium protection.

32. The slave electronic circuit claimed in claim 27 wherein said processor is further operable to perform a power management process in response to the received schedule.

33. A slave electronic circuit comprising:

a storage representing a wireless networking process compatible with WiFi and combined with a data transfer process compatible with USB;

a wireless modem compatible with WiFi; and

a processor coupled with said storage and with said wireless modem and operable to execute the wireless networking process to establish the circuit as a WiFi device instead of an access point AP, and also establish the circuit as a USB-like slave function in wireless.

34. The slave electronic circuit claimed in claim 33 wherein WiFi Direct involves beacons and said processor is responsive to said wireless networking process to detect the beacons and further to detect a scheduling command for the USB-compatible data transfer process during each said beacon.

35. The slave electronic circuit claimed in claim 34 wherein said processor is responsive to the detected scheduling command to perform USB-like data transfer in and out depending on the scheduling command in such beacon and using said wireless modem.

36. The slave electronic circuit claimed in claim 33 wherein said processor is operable to detect a polling operation via said wireless modem and to respond to the polling operation to send a request for USB-like access through said wireless modem.

37. The slave electronic circuit claimed in claim 33 wherein said processor is operable to detect a medium protection signal through said wireless modem, whereby power management is facilitated.

38. The slave electronic circuit claimed in claim 33 wherein said processor is operable to detect a beacon-based schedule of access times and corresponding slave station identifications for a wireless form of USB inside of WiFi and to schedule USB-like slave data transfer operations at the access times scheduled for its particular slave station identification.

39. The slave electronic circuit claimed in claim 33 wherein said processor is operable to discover and to stream content by scheduled USB-like operations while wirelessly networking by WiFi generally.

40. The slave electronic circuit claimed in claim 33 further comprising a peripheral coupled with said processor to play content, and wherein the storage includes a WiFi Direct protocol for peer-to-peer wireless networking operations coupled together with the data transfer process compatible with USB so that said processor is operable to attach the peripheral wirelessly whereby to receive stream of data in USB-like form and to render the stream of data into content for said peripheral to play.

41. A wireless master process comprising:

a wireless collision avoidance networking process involving collision avoidance overhead;

a schedulable serial data transfer process combined with the wireless collision avoidance networking process, and including a scheduling process to establish and wirelessly transmit a schedule in advance for subsequent serial data transfers involving distinct station identifications;

protecting the wireless medium in a manner that will at least piecewise encompass the scheduled serial data transfers; and

wirelessly executing the serial data transfers according to the schedule so as to avoid at least some of the collision avoidance overhead.

42. The wireless master process claimed in claim 41 wherein the scheduling process includes transmitting periodic beacon signals with the schedule entirely in a given beacon signal outside an interval between the periodic beacon signals, whereby to wirelessly transmit the schedule.

43. A wireless slave process comprising:

a wireless collision avoidance networking process involving collision avoidance overhead and combined with a schedule-driven serial data transfer process;

wirelessly receiving a schedule for specifying serial data transfers and their station identifications; and

executing any serial data transfers scheduled by a such station identification for the slave process itself inside the wireless networking process and according to the schedule so as to obviate at least some of the collision avoidance overhead.

44. The wireless slave process claimed in claim 43 wherein the wireless collision avoidance networking process involves detection of periodic beacon signals, and the slave process obtaining an entire such schedule from a given beacon signal alone.

45. The wireless slave process claimed in claim 43 further comprising wirelessly receiving a medium protection control signal and responsively preventing transmission except at a scheduled time for which the specified station identification has identified the slave process itself for serial data transfer under medium protection.