Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance

• US 20110193591A1
• Filed: 04/18/2011
• Published: 08/11/2011
• Est. Priority Date: 09/08/2003
• Status: Active Grant

• Current Assignee: Ramubs Inc.
• Original Assignee: Rambus Inc.
• Inventors: Nguyen, Huy M., Gadde, Vijay, Lau, Benedict
• Granted Patent: US 8,278,968 B2
• Time in Patent Office: Days
• US Class Current: 326/30
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance
• CPC Class Codes: H03K 19/01 Modifications for accelerating switching
• CPC Class Codes: H03K 21/08 Output circuits
• CPC Class Codes: H03K 5/24 the characteristic being amplitude
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines

Abstract

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Claims

1. A termination control circuit comprising:

a first node to receive a reference voltage;

a second node to couple to a reference resistance;

an adjustable resistor exhibiting an adjustable impedance responsive to an impedance-control signal;

a comparator having a first input coupled to the first node to receive the reference voltage, a second input coupled to the second node via the adjustable resistor, and a comparator output;

a transistor coupled between the second input and a supply terminal; and

a counter operatively coupled between the comparator output and the adjustable resistor, the counter to update the impedance-control signal responsive to an output from the comparator.

2. The termination control circuit of claim 1, wherein the counter is operatively coupled between the comparator and the adjustable resistor via a latch, the latch to capture the output from the comparator.

3. The termination control circuit of claim 2, further comprising a filter, wherein the latch is operatively coupled to the comparator via the filter.

4. The termination control circuit of claim 1, wherein the transistor selectively disables current flow through the adjustable resistor.

5. The termination control circuit of claim 1, wherein the transistor includes a control terminal, and wherein the output from the comparator controls a voltage on the control terminal.

6. The termination control circuit of claim 5, further comprising a second counter coupled between the comparator and the control terminal.

7. The termination control circuit of claim 6, wherein the second counter increments or decrements in response to the output from the comparator.

8. The termination control circuit of claim 7, wherein the second counter stores a count that determines a current through the adjustable resistor.

9. The termination control circuit of claim 7 instantiated on an integrated circuit device with a driver to drive a signal from the integrated circuit device via a signal pad, wherein the second counter stores a count that establishes a drive current through the driver.

10. The termination control circuit of claim 1, wherein at least one of the first node and the second node comprises a pad of an integrated circuit.

11. The termination control circuit of claim 1, further comprising termination elements coupled to the counter to receive the impedance-control signal.

12. The termination control circuit of claim 11 instantiated on an integrated circuit device with a receiver circuit including a differential amplifier to receive a pair of complementary signals via respective first and second signal pads, wherein each of the signal pads is coupled to a DC voltage via a respective one of the termination elements.

13. An integrated circuit device comprising:

a receiver circuit including a differential amplifier to receive a pair of complementary input signals via respective first and second nodes;

a first termination element, exhibiting a first impedance, coupled to the first node and including a first impedance control input;

a second termination element, exhibiting a second impedance, coupled to the second node and including a second impedance control input; and

a control circuit having;

an adjustable reference element to develop a reference impedance; and

a feedback path to apply a calibration signal to the adjustable reference element to set the reference impedance;

wherein the feedback path is coupled to the first and second impedance control inputs to set the first and second impedances.

14. The integrated circuit of claim 13, wherein the control circuit includes a comparator having a first input coupled to a first node to receive a reference voltage, a second input coupled to a second node via the adjustable reference element, and a comparator output coupled to an input to the feedback path.

15. The integrated circuit of claim 14, further comprising a transistor coupled between the second input and a supply terminal.

16. The integrated circuit of claim 15, wherein the transistor selectively disables current flow through the reference element.

17. The integrated circuit of claim 15, wherein the transistor includes a control terminal operatively coupled to the comparator output.

18. The integrated circuit of claim 17, wherein the control terminal is operatively coupled to the comparator output via a signal path comprising a latch.

19. The integrated circuit of claim 14, wherein the control circuit includes a counter to store the calibration signal.

20. The integrated circuit of claim 19, further comprising a latch between the comparator output and the counter, the latch to capture an output from the comparator.

21. The integrated circuit of claim 20, wherein the counter updates the calibration signal in response to the captured output from the comparator.

22. The integrated circuit of claim 13, further comprising a first circuit pad coupled to the first node and a second circuit pad coupled to the second node, and a third circuit pad coupled to the adjustable reference element.

23. The integrated circuit of claim 13, further comprising a signal driver coupled to the control circuit to receive the calibration signal, the signal driver to provide a drive current proportional to the calibration signal.

24. The integrated circuit of claim 23, wherein the control circuit further comprises a counter coupled to the feedback path to store a count that determines the drive current.