Three dimensional structure memory

• US 20110198672A1
• Filed: 05/27/2010
• Published: 08/18/2011
• Est. Priority Date: 04/04/1997
• Status: Active Grant

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: Glenn J. Leedy
• Inventors: Leedy, Glenn J.
• Granted Patent: US 8,653,672 B2
• Time in Patent Office: Days
• US Class Current: 257/211
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. An integrated circuit structure comprising:

a first substrate comprising a first surface having interconnect contacts; and

a substantially flexible second substrate comprising a first surface and a second surface at least one of which has interconnect contacts, wherein the second surface is opposite the first surface and wherein the second surface of the second substrate is polished; and

conductive paths between the interconnect contacts of the first surface of the first substrate and said one of the first surface of the second substrate and the second surface of the second substrate;

wherein the first surface of the first substrate and one of the first surface of the second substrate and the second surface of the second substrate are bonded in a stacked relationship, the first substrate overlapping at least a majority of the second substrate.

2. The integrated circuit structure of claim 1, wherein the second substrate is one of a thin monocrystalline semiconductor substrate and a thin polycrystalline semiconductor substrate.

3. The integrated circuit structure of claim 1, wherein circuitry is formed on the second substrate, said circuitry comprising one of active circuitry and passive circuitry.

4. The integrated circuit structure of claim 1, wherein circuitry is formed on the second substrate comprising both active circuitry and passive circuitry.

5. The integrated circuit structure of claim 1, wherein the first substrate is a substrate having circuitry formed thereon.

6. The integrated circuit structure of claim 1, further comprising:

at least one additional thin substrate having circuitry formed thereon;

a first of said at least one additional thin substrate being bonded to the second substrate and any additional thin substrates being bonded to a directly adjacent additional thin substrate; and

conductive paths formed between said first of said at least one additional thin substrate and at least one of said first and second substrates and also between each additional thin substrate and at least one of said substrates of the integrated circuit structure.

7. The integrated circuit structure of claim 1, wherein the first substrate is a non-semiconductor material.

8. An integrated circuit structure comprising:

a first substrate having topside and bottomside surfaces, wherein the topside surface of the first substrate has interconnect contacts;

a substantially flexible second substrate having topside and bottom-side surfaces, wherein at least one of the topside surface and the bottom-side surface of the second substrate has interconnect contacts, and wherein the bottomside surface of the second substrate is polished;

wherein a major portion of the topside surface of the first substrate and one of the topside surface of the second substrate and the bottom-side surface of the second substrate are bonded in a stacked relationship; and

conductive paths between the interconnect contacts on the topside surface of the first substrate and said one of the topside surface of the second substrate and the bottomside surface of the second substrate, the conductive paths providing electrical connections between the first substrate and the second substrate;

wherein the first substrate overlaps at least a majority of the second substrate.

9. The integrated circuit structure of claim 8, wherein selected ones of said interconnect contacts of said topside surface of said first substrate are in electrical contact with selected ones of the interconnect contacts of said bottom-side surface of said second substrate so as to form said electrical connections.

10. The integrated circuit structure of claim 8, further comprising:

at least one additional thin substrate having circuitry formed thereon;

a first of said at least one additional thin substrate being bonded to the second substrate and any additional thin substrates being bonded to a directly adjacent additional thin substrate; and

conductive paths formed between said first of said at least one additional thin substrate and at least one of said first and second substrates and also between each additional thin substrate and at least one of said substrates of the integrated circuit structure.

11. The integrated circuit structure of claim 8, wherein the first substrate and the second substrate are the same size or overlap each other completely.

12. The integrated circuit structure of claim 8, wherein at least one of the first and second substrates comprises a low stress dielectric layer, wherein the low stress dielectric layer is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a stress of about 5×

10⁸ dynes/cm² or less.

13. The integrated circuit structure of claim 8, further comprising memory circuitry on the second substrate, wherein a portion of the memory circuitry is redundant memory circuitry.

14. An integrated circuit structure comprising:

a first substrate having a first and second surface;

a second substrate having a first and second surface, wherein said second surfaces of the first and second substrates are opposite to said first surfaces;

wherein at least one of the first substrate and the second substrate is thin and substantially flexible, thereby providing at least one thin substrate, and wherein the second surface of the at least one thin substrate is polished;

wherein the first surface of the first substrate and a major portion of one of the first surface of the second substrate and the second surface of the second substrate are bonded in a stacked relationship by at least one bond, wherein the at least one bond secures a major portion of the second substrate to the first substrate; and

conductive paths between at least two of the first surface of the first substrate and the first and second surfaces of the second substrate, wherein the first substrate overlaps at least a majority of the second substrate.

15. The integrated circuit structure of claim 14, wherein the first substrate and the second substrate are the same size or overlap each other completely.

16. The integrated circuit structure of claim 14, wherein at least one of the first and second substrates comprises a low stress dielectric layer, wherein the low stress dielectric layer is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a stress of about 5×

10⁸ dynes/cm² or less.

17. The integrated circuit structure of claim 14, further comprising memory circuitry on the second substrate, wherein a portion of the memory circuitry is redundant memory circuitry.

18. The integrated circuit structure of claim 14, wherein at least two of:

the first substrate is a non-semiconductor material;

at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×

10⁸ dynes/cm² or less;

the dielectric is at least one of silicon dioxide and an oxide of silicon;

the second substrate has one of logic circuitry and memory circuitry formed thereon;

the second substrate has microprocessor circuitry formed thereon;

the second substrate has reconfiguration circuitry formed thereon;

the second substrate has redundant circuitry formed thereon;

the second substrate has a thickness of about 1 to 8 microns;

the second substrate has a thickness of about 10 microns or less;

the first substrate and the second substrate are bonded by at least one diffusion bond;

at least one of the substrates is substantially flexible;

the second substrate is substantially flexible;

at least one conductive path passes through the first substrate;

at least one conductive path passes through the second substrate;

at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate;

at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate;

conductive paths are formed between and within overlapping portions of bonded surfaces of the first substrate and second substrate;

the second surface of the second substrate has an oxide layer formed thereon;

at least one conductive path passes through at least one of the first substrate and the second substrate and the conductive path is insulated by an insulating material from said substrate.

19. The integrated circuit structure of claim 14, wherein at least three of:

the first substrate is a non-semiconductor material;

at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×

10⁸ dynes/cm² or less;

the dielectric is at least one of silicon dioxide and an oxide of silicon;

the second substrate has one of logic circuitry and memory circuitry formed thereon;

the second substrate has microprocessor circuitry formed thereon;

the second substrate has reconfiguration circuitry formed thereon;

the second substrate has redundant circuitry formed thereon;

the second substrate has a thickness of about 1 to 8 microns;

the second substrate has a thickness of about 10 microns or less;

the first substrate and the second substrate are bonded by at least one diffusion bond;

at least one of the substrates is substantially flexible;

the second substrate is substantially flexible;

at least one conductive path passes through the first substrate;

at least one conductive path passes through the second substrate;

at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate;

at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate;

conductive paths are formed between and within overlapping portions of bonded surfaces of the first substrate and second substrate;

the second surface of the second substrate has an oxide layer formed thereon;

at least one conductive path passes through at least one of the first substrate and the second substrate and the conductive path is insulated by an insulating material from said substrate.

20. An integrated circuit structure comprising:

a plurality of substrates having first and second surfaces and arranged in a stacked relationship, wherein at least one of the substrates is substantially flexible having a polished second surface and one or more integrated circuits formed on the first surface; and

at least one interconnection between two of the plurality of substrates;

wherein one of the plurality of substrates overlaps a majority of the substantially flexible substrate.

21. The integrated circuit structure of claim 20, wherein at least one of the integrated circuits comprises redundant circuitry.

22. The integrated circuit structure of claim 20, wherein at least one conductive path passes through at least one of the plurality of substrates and the conductive path is insulated by an insulating material from said substrate.