SEMICONDUCTOR MEMORY DEVICE, DRIVING METHOD THEREOF, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

• US 20110205774A1
• Filed: 02/10/2011
• Published: 08/25/2011
• Est. Priority Date: 02/19/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: TAKEMURA, Yasuhiko
• Granted Patent: US 8,593,857 B2
• Time in Patent Office: Days
• US Class Current: 365/72
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A matrix is formed using a plurality of memory cells in each of which a drain of the writing transistor is connected to a gate of a reading transistor and one electrode of a capacitor. A gate of the writing transistor, a source of the writing transistor, a source of the reading transistor, and a drain of the reading transistor are connected to a writing word line, a writing bit line, a reading bit line, and a bias line, respectively. The other electrode of the capacitor is connected to a reading word line. In order to decrease the number of wirings, the writing bit line is substituted for the reading bit line. The reading bit line is formed so as to be embedded in a groove-like opening formed over a substrate.

Claims

1. A matrix-type semiconductor memory device comprising:

a first line;

a second line;

a third line;

a fourth line; and

a plurality of memory cells,

wherein the first line is parallel to the second line,

wherein the third line is parallel to the fourth line,

wherein at least one of the plurality of memory cells includes a first transistor, a second transistor, and a capacitor,

wherein a drain of the first transistor is connected to a gate of the second transistor and one electrode of the capacitor,

wherein a gate of the first transistor is connected to the first line,

wherein a source of the first transistor and a source of the second transistor are connected to the third line,

wherein a drain of the second transistor is connected to the fourth line,

wherein the other electrode of the capacitor is connected to the second line, and

wherein the third line is provided between the first line and the substrate.

2. The semiconductor memory device according to claim 1, wherein the fourth line comprises the same material as the third line.

3. The semiconductor memory device according to claim 1, wherein the gate of the second transistor comprises the same material as the third line.

4. The semiconductor memory device according to claim 1, wherein the first line, the second line, the third line, the fourth line and the plurality of memory cells are provided over a semiconductor substrate.

5. The semiconductor memory device according to claim 1, wherein the first line is orthogonal to the third line.

6. The semiconductor memory device according to claim 1, wherein a width of the second line is greater than or equal to 0.5 times and less than or equal to 1.5 times a width of the first line.

7. A matrix-type semiconductor memory device comprising:

a first line;

a second line;

a third line;

a fourth line; and

a plurality of memory cells,

wherein the first line is parallel to the second line,

wherein the third line is parallel to the fourth line,

wherein at least one of the plurality of memory cells includes a first transistor, a second transistor, and a capacitor,

wherein a drain of the first transistor is connected to a gate of the second transistor and one electrode of the capacitor,

wherein a gate of the first transistor is connected to the first line,

wherein a source of the first transistor and a source of the second transistor are connected to the third line,

wherein a drain of the second transistor is connected to the fourth line,

wherein the other electrode of the capacitor is connected to the second line,

wherein the third line is provided between the first line and the substrate, and

wherein the gate of the second transistor is in contact with a semiconductor layer of the first transistor.

8. The semiconductor memory device according to claim 7, wherein the fourth line comprises the same material as the third line.

9. The semiconductor memory device according to claim 7, wherein the gate of the second transistor comprises the same material as the third line.

10. The semiconductor memory device according to claim 7, wherein the first line, the second line, the third line, the fourth line and the plurality of memory cells are provided over a semiconductor substrate.

11. The semiconductor memory device according to claim 7, wherein the first line is orthogonal to the third line.

12. The semiconductor memory device according to claim 7, wherein a width of the second line is greater than or equal to 0.5 times and less than or equal to 1.5 times a width of the first line.

13. A matrix-type semiconductor memory device comprising:

a first line;

a second line;

a third line;

a fourth line; and

a plurality of memory cells,

wherein the first line is parallel to the second line,

wherein the third line is parallel to the fourth line,

wherein at least one of the plurality of memory cells includes a first transistor, a second transistor, and a capacitor,

wherein a drain of the first transistor is connected to a gate of the second transistor and one electrode of the capacitor,

wherein a gate of the first transistor is connected to the first line,

wherein a source of the first transistor and a source of the second transistor are connected to the third line,

wherein a drain of the second transistor is connected to the fourth line,

wherein the other electrode of the capacitor is connected to the second line,

wherein the third line is provided between the first line and the substrate, and

wherein the third line is in contact with a semiconductor layer of the first transistor.

14. The semiconductor memory device according to claim 13, wherein the fourth line comprises the same material as the third line.

15. The semiconductor memory device according to claim 13, wherein the gate of the second transistor comprises the same material as the third line.

16. The semiconductor memory device according to claim 13, wherein the first line, the second line, the third line, the fourth line and the plurality of memory cells are provided over a semiconductor substrate.

17. The semiconductor memory device according to claim 13, wherein the first line is orthogonal to the third line.

18. The semiconductor memory device according to claim 13, wherein a width of the second line is greater than or equal to 0.5 times and less than or equal to 1.5 times a width of the first line.

19. A matrix-type semiconductor memory device comprising:

a first line;

a second line;

a third line;

a fourth line; and

a plurality of memory cells,

wherein the first line is parallel to the second line,

wherein the third line is parallel to the fourth line,

wherein at least one of the plurality of memory cells includes a first transistor, a second transistor, and a capacitor,

wherein a drain of the first transistor is connected to a gate of the second transistor and one electrode of the capacitor,

wherein a gate of the first transistor is connected to the first line,

wherein a source of the first transistor and a source of the second transistor are connected to the third line,

wherein a drain of the second transistor is connected to the fourth line,

wherein the other electrode of the capacitor is connected to the second line,

wherein the third line is provided between the first line and the substrate,

wherein the gate of the second transistor is in contact with a semiconductor layer of the first transistor, and

wherein the third line is in contact with the semiconductor layer of the first transistor.

20. The semiconductor memory device according to claim 19, wherein the fourth line comprises the same material as the third line.

21. The semiconductor memory device according to claim 19, wherein the gate of the second transistor comprises the same material as the third line.

22. The semiconductor memory device according to claim 19, wherein the first line, the second line, the third line, the fourth line and the plurality of memory cells are provided over a semiconductor substrate.

23. The semiconductor memory device according to claim 19, wherein the first line is orthogonal to the third line.

24. The semiconductor memory device according to claim 19, wherein a width of the second line is greater than or equal to 0.5 times and less than or equal to 1.5 times a width of the first line.

25. A method for driving a matrix-type semiconductor memory device including a first line, a second line, a third line, a fourth line, and a plurality of memory cells,

wherein the first line is parallel to the second line,

wherein the third line is parallel to the fourth line,

wherein at least one of the plurality of memory cells includes a first transistor, a second transistor, and a capacitor,

wherein a drain of the first transistor is connected to a gate of the second transistor and one electrode of the capacitor,

wherein a gate of the first transistor is connected to the first line,

wherein a source of the first transistor and a source of the second transistor are connected to the third line,

wherein a drain of the second transistor is connected to the fourth line,

wherein the other electrode of the capacitor is connected to the second line, and

wherein the third line is provided between the first line and the substrate.

wherein potential of the fourth line is higher than potential of the third line at the time of writing data.

26. A method for manufacturing a semiconductor device comprising the steps of:

forming a first gate insulating film over a substrate;

forming a first line over the first gate insulating film;

forming a groove-like opening not in contact with the first line;

depositing a conductive material in the groove-like opening;

planarizing the conductive material by etching to form a second line;

forming a semiconductor layer in contact with the first line and the second line; and

forming a second gate insulating film over the semiconductor layer.