DYNAMICALLY ALLOCATING NUMBER OF BITS PER CELL FOR MEMORY LOCATIONS OF A NON-VOLATILE MEMORY

• US 20110208896A1
• Filed: 02/25/2010
• Published: 08/25/2011
• Est. Priority Date: 02/25/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Wakrat, Nir J., Toelkes, Tahoma M.
• Granted Patent: US 8,402,243 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Systems and methods are provided for dynamically allocating a number of bits per cell to memory locations of a non-volatile memory (“NVM”) device. In some embodiments, a host may determine whether to store data in the NVM device using SLC programming or MLC programming operations. The host may allocate an erased block as an SLC block or MLC block based on this determination regardless of whether the erased block was previously used as an SLC block, MLC block, or both. In some embodiments, to dynamically allocate a memory location as SLC or MLC, the host may provide an address vector to the NVM package, where the address vector may specify the memory location and the number of bits per cell to use for that memory location.

Claims

1. A method of accessing a memory location of a non-volatile memory device, the method comprising:

dynamically allocating a first number of bits per cell to the memory location;

accessing the memory location based on the first number of bits per cell;

erasing the memory location;

dynamically assigning a second number of bits per cell to the memory location; and

accessing the memory location based on the second number of bits per cell.

2. The method of claim 1, wherein the dynamically assigning is performed independently of the dynamically allocating.

3. The method of claim 1, further comprising:

creating a mapping between the memory location and the first number of bits per cell responsive to the dynamically allocating; and

updating the mapping to map the memory location to the second number of bits per cell responsive to the dynamically assigning.

4. The method of claim 1, further comprising:

obtaining first data to store in the memory location, wherein the dynamically allocating is based on characteristics of the first data; and

obtaining second data to store in the memory location subsequent to erasing the first data from the memory location, wherein the dynamically assigning is based on characteristics of the second data.

5. The method of claim 1, wherein the first number is one, and wherein the second number is more than one.

6. The method of claim 1, wherein the first number is more than one, and wherein the second number is one.

7. A method of storing information in a non-volatile memory device, the method comprising:

selecting an erased memory location of the non-volatile memory device in which to store the information;

deciding on a number of bits per cell to use for the erased memory location; and

programming the information into the erased memory location of the non-volatile memory device based on the deciding.

8. The method of claim 7, further comprising:

generating an address vector indicating the memory location of the non-volatile memory device and a result of the deciding, wherein the programming is based on the generating.

9. The method of claim 7, wherein:

the non-volatile memory device comprises flash memory having a plurality of blocks;

the selecting comprises choosing at least one page from one of the blocks; and

the deciding comprises determining whether to dynamically allocate the one of the blocks as a SLC block or a MLC block.

10. The method of claim 7, wherein the deciding comprises:

determining at least one of a desired reliability, a desired storage speed, and a desired performance associated with the data; and

deciding on the number of bits per cell

to use based on the determining.

11. The method of claim 7, further comprising:

responsive to the deciding, marking a metadata portion of the memory location to specify the number of bits per cell.

12. The method of claim 7, wherein the programming comprises:

choosing a page programming order based on the deciding; and

programming the information into the memory location using the page programming order.

13. A method of retrieving information from a non-volatile memory (“

NVM”

) package, wherein the NVM package comprises at least one NVM device, the method comprising;

identifying, at a host, a memory location of the at least one NVM device in which the information is stored;

determining, at the host, a number of bits per cell associated with the memory location;

providing, from the host to the NVM package, an address vector indicating the memory location and a result of the determining;

reading, at the NVM package, the information from the memory location of the at least one NVM device based on address vector.

14. The method of claim 13, further comprising:

mapping each of a plurality of memory locations in the at least one NVM device to a number of bits per cell, wherein the determining is performed based on the mapping.

15. The method of claim 13, wherein the NVM package is a managed NVM package comprising a NVM controller, and wherein the NVM controller is configured to use the address vector to perform the reading.

16. The method of claim 13, wherein the NVM package is a raw NVM package comprising an address decoder, and wherein the address decoder is configured to use the address vector to perform the reading.

17. The method of claim 13 further comprising:

verifying, using a metadata portion of the information, that the determining resulted in the correct number of bits per cell.

18. A memory system comprising:

a managed non-volatile memory (“

NVM”

) package comprising;

at least one NVM device, and

a NVM controller configured to access the at least one NVM device; and

a host controller configured to direct the NVM controller to access a memory location of the at least NVM device using an address vector, wherein the address vector indicates a number of bits per cell to use when accessing the memory location.

19. The memory system of claim 18, wherein one bit of the address vector is allocated for indicating the number of bits per cell, and wherein a first value of the one bit indicates one bit per cell and a second value of the one bit indicates more than one bit per cell.

20. The memory system of claim 18, wherein at least two bits of the address vector are allocated for indicating the number of bits per cell.

21. The memory system of claim 18, wherein the host controller comprises a processor operating under control of a memory driver and other software modules, and wherein the processor is configured to:

obtain, at the memory driver from the other software modules, a request to access the at least one NVM device;

select the memory location;

decide on the number of bits per cell to use when accessing the memory location; and

generate the address vector based on the selected memory location and the decided number of bits per cell.

22. The memory system of claim 18, wherein the host controller is further configured to:

maintain a mapping between the physical address and the number of bits per cell.

23. The memory system of claim 18, wherein the NVM controller is further configured to:

access the at least one NVM device based on the address vector received from the host controller; and

maintain a mapping between the physical address and the number of bits per cell.

24. The memory system of claim 18, wherein the managed NVM package comprises a managed NAND package.

25. A memory system comprising:

a raw non-volatile memory (“

NVM”

) package comprising;

at least one NVM device comprising a plurality of blocks,

an address input for receiving a selection of one of the plurality of blocks, and

a SLC/MLC input for receiving an indication of a number of bits per cell associated with the one of the plurality of blocks selected through the address input; and

a host controller operable to access at least one of the plurality of blocks using the address input and the SLC/MLC input.

26. The memory system of claim 25, wherein raw NVM package further comprises an address decoder configured to interpret an address received from the address input based on an SLC/MLC indicator received from the SLC/MLC input.

27. The memory system of claim 25, wherein the NVM device comprises NAND flash memory.