INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF

• US 20110210436A1
• Filed: 02/26/2010
• Published: 09/01/2011
• Est. Priority Date: 02/26/2010
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Kuan, Heap Hoe, Chow, Seng Guan, Huang, Rui, Goh, Hin Hwa
• Granted Patent: US 8,624,364 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45014 Ribbon connectors, e.g. rectangular cross-section
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83101 as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/206 : Length ranges
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; attaching a base barrier on the base substrate adjacent a base perimeter thereof; mounting a stack substrate over the base substrate, the stack substrate having a stack substrate aperture with the stack substrate having an inter-substrate connector thereon; and dispensing a connector underfill through the stack substrate aperture encapsulating the inter-substrate connector, overflow of the connector underfill prevented by the base barrier.

Claims

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a base substrate;

attaching a base integrated circuit on the base substrate;

attaching a base barrier on the base substrate adjacent a base perimeter thereof;

mounting a stack substrate over the base substrate, the stack substrate having a stack substrate aperture with the stack substrate having an inter-substrate connector thereon; and

dispensing a connector underfill through the stack substrate aperture encapsulating the inter-substrate connector, overflow of the connector underfill prevented by the base barrier.

2. The method as claimed in claim 1 wherein mounting the stack substrate includes mounting the stack substrate having a stack barrier adjacent a stack perimeter thereof.

3. The method as claimed in claim 1 wherein dispensing the connector underfill includes dispensing the connector underfill adjacent the base barrier.

4. The method as claimed in claim 1 wherein dispensing the connector underfill includes dispensing the connector underfill between the base substrate and the stack substrate.

5. The method as claimed in claim 1 further comprising mounting a top integrated circuit package over the stack substrate, the entirety of the top integrated circuit package adjacent the stack substrate aperture.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a base substrate;

attaching a base integrated circuit on the base substrate;

attaching a base barrier on the base substrate adjacent a base perimeter thereof;

mounting a stack substrate over the base substrate, the stack substrate having a stack substrate aperture with the stack substrate having an inter-substrate connector thereon and the inter-substrate connector between the base barrier and the base integrated circuit; and

dispensing a connector underfill through the stack substrate aperture encapsulating the inter-substrate connector, overflow of the connector underfill prevented by the base barrier.

7. The method as claimed in claim 6 wherein:

mounting the stack substrate includes mounting the stack substrate having a stack substrate protrusion; and

dispensing the connector underfill includes dispensing the connector underfill over a portion of the stack substrate protrusion.

8. The method as claimed in claim 6 further comprising removing a portion of the stack substrate and a portion of the connector underfill, an outer edge of the stack substrate substantially intersected by an extent of the connector underfill.

9. The method as claimed in claim 6 wherein mounting the stack substrate includes mounting the stack substrate having a stack substrate open region adjacent the stack substrate aperture.

10. The method as claimed in claim 6 wherein attaching the base integrated circuit on the base substrate includes attaching a flip chip on the base substrate.

11. An integrated circuit packaging system comprising:

a base substrate;

a base integrated circuit on the base substrate;

a base barrier on the base substrate adjacent a base perimeter thereof;

a stack substrate over the base substrate, the stack substrate having a stack substrate aperture with the stack substrate having an inter-substrate connector thereon; and

a connector underfill through the stack substrate aperture encapsulating the inter-substrate connector, overflow of the connector underfill prevented by the base barrier.

12. The system as claimed in claim 11 wherein the stack substrate includes the stack substrate having a stack barrier adjacent a stack perimeter thereof.

13. The system as claimed in claim 11 wherein the connector underfill is adjacent the base barrier.

14. The system as claimed in claim 11 wherein the connector underfill is between the base substrate and the stack substrate.

15. The system as claimed in claim 11 further comprising a top integrated circuit package over the stack substrate, the entirety of the top integrated circuit package adjacent the stack substrate aperture.

16. The system as claimed in claim 11 wherein the inter-substrate connector is between the base barrier and the base integrated circuit.

17. The system as claimed in claim 16 wherein the stack substrate includes a stack substrate protrusion, the connector underfill over a portion of the stack substrate protrusion.

18. The system as claimed in claim 16 wherein the connector underfill includes an outer edge of the stack substrate substantially intersected by an extent of the connector underfill.

19. The system as claimed in claim 16 wherein the stack substrate includes a stack substrate open region adjacent the stack substrate aperture.

20. The system as claimed in claim 16 wherein the base integrated circuit includes a flip chip on the base substrate.