DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEATH THE INSULATING LAYER

• US 20110215860A1
• Filed: 01/14/2011
• Published: 09/08/2011
• Est. Priority Date: 03/03/2010
• Status: Active Grant

• Current Assignee: Soitec S.A.
• Original Assignee: Soitec S.A.
• Inventors: Mazure, Carlos, Ferrant, Richard
• Granted Patent: US 8,432,216 B2
• Time in Patent Office: Days
• US Class Current: 327/537
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel

Abstract

The invention provides a data-path cell specifically adapted to its environment for use in an integrated circuit produced on a semiconductor-on-insulator (SeOI) substrate. The data-path cell includes an array of field-effect transistors, each transistor having a source region, a drain region and a channel region formed in the thin semiconductor layer of the SeOI substrate, and further having a front gate control region formed above the channel region. In particular, one or more transistors of the data-path cell further includes a back gate control region formed in the bulk substrate beneath the channel region and configured so as to modify the performance characteristics of the transistor in dependence on its state of bias. Also, an integrated circuit including one or more of the data-path cells and methods for designing or driving these data-path cells.

Claims

1. A data-path cell produced on a semiconductor-on-insulator substrate comprising a thin layer of semiconductor material separated from a bulk substrate by an insulating layer, the cell comprising an array of field-effect transistors (FETs), each transistor comprising:

in the thin layer of semiconductor material, a source region, a drain region and a channel region interposed between the source and drain regions,

above the channel region, a front gate control region; and

one or more back gate control regions formed in the bulk substrate beneath the channel region of one or more FETs, with the back gate control region associated with a particular transistor being configured and positioned so that the performance characteristics of that transistor varies in dependence on a bias applied to the back gate control region,

wherein the size and configuration of the FETs and the size and configuration of the back gate control regions are selected so that the data path cell is specifically adapted for use in the environment of a particular integrated circuit.

2. The cell of claim 1, further comprising a back gate line sized and configured so as to apply a bias to the back gate control regions of one or more selected FETs connected thereto, with the back gate line extending into the bulk substrate beneath the insulating layer.

3. The cell of claim 1, wherein one or more of the back gate control regions is isolated from the bulk substrate by a well of opposite conductivity.

4. The cell of claim 1, wherein one or more of the back gate control regions has a conductivity that is essentially the same as that of the channel region.

5. The cell of claim 1, wherein the channel regions, the front control gate regions and the back gate control regions of the one or more FETs are sized and configured so that the associated FETs have a selected combination of reduced footprint and increased performance when compared to similar FETs without any back gate control regions.

6. The cell of claim 1, wherein the channel regions and the front control gate regions of one of more of the FETs are sized such that so that the cell is specifically adapted for use in the environment of a particular integrated circuit.

7. The cell of claim 2, further comprising a plurality of back gate lines sized and configured so as to apply a bias to the back gate control regions of one or more FETs connected thereto, with each FET being connected to at most one back gate line.

8. The cell of claim 2, wherein the array of FETs is arranged into one or more rows of FETs or into one or more columns of FETs, and wherein the back gate line connects to the back gate control regions of the FETs along one of the rows or along one of the columns.

9. The cell of claim 2, wherein the array of FETs further comprises:

an input stage including one or more FETs to which are connected input lines into the cell; and

an output stage including one or more FETs to which are connected output lines from the cell, and

wherein the back gate line connects to the back gate control regions of the FETs of the input stage, or to the back gate control regions of the FETs of the output stage, or to the back gate control regions of the FETs of both the input and the output stages.

10. An integrated circuit produced on a semiconductor-on-insulator substrate comprising one or more of the data-path cells of claim 1.

11. The circuit of claim 10, wherein the data-path cells are arranged in one or more rows along a first direction, and when multiple rows are present at least one of the rows is arranged along a different second direction.

12. The circuit of claim 11, further comprising one or more back gate control lines, each back gate control line connecting the back gate control regions of some or all of the FETs in the data-path cells along one row.

13. The circuit of claim 12, wherein the data-path cells are configured with input and output stages, each stage comprising one or more FETs, and wherein one or more of the back gate control lines connects to the back gate control regions of FETs of input stages of the data-path cells along at least one row, or to back gate control regions of FETs of output stages of the data-path cells along at least one row.

14. A method of driving a data-path cell of claim 1 comprising applying two or more different bias voltages to the back gate control regions of one or more FETs,

wherein at least one bias voltage is selected to reduce leakage currents, and

wherein at least one other bias voltage is selected to increase conduction currents.

15. The method of claim 14, wherein the back gate control regions of one or more FETs are biased to a first bias voltage when in the off-state, and wherein the back gate control regions of one or more FETs are biased to a different second bias voltage when in the on-state, with the at least one bias voltage selected to increase conduction currents applied to one or more FETs that provide output from the data-path cell.

16. A method of designing a data-path cell of claim 1 which comprises specifically adapting the cell to an environment of a particular integrated circuit by

selecting the sizes of the channel regions and the front control gate regions of one of more of the FETs in order to achieve selected capacitance thereof;

and

providing the back gate control regions for one or more FETs in order to achieve selected conductance thereof when in an on-state;

wherein the capacitance and the conductance are selected in dependence on footprint and performance characteristics of the particular integrated circuit environment.

17. The method of claim 16, wherein the footprint and performance characteristics of the particular integrated circuit environment include one of:

a capacitance that is reduced by up to about 33% and conductance that is not reduced;

an operating speed that is increased about 20% and a power consumption that is reduced about 20% in the active mode and by about one decade in the inactive mode, and wherein the footprint is reduced about 20%; and

an operating speed that is increased between about 30 and 50%.